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annotate test/CodeGen/AMDGPU/shrink-carry.mir @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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121
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1 # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s
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2
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3 # GCN-LABEL: name: subbrev{{$}}
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4 # GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec
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5
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6 ---
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7 name: subbrev
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8 tracksRegLiveness: true
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9 registers:
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10 - { id: 0, class: vgpr_32 }
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11 - { id: 1, class: vgpr_32 }
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12 - { id: 2, class: vgpr_32 }
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13 - { id: 3, class: sreg_64_xexec }
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14 - { id: 4, class: vgpr_32 }
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15 - { id: 5, class: sreg_64_xexec }
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16 body: |
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17 bb.0:
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18
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19 %0 = IMPLICIT_DEF
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20 %1 = IMPLICIT_DEF
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21 %2 = IMPLICIT_DEF
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22 %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
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23 %4, %5 = V_SUBBREV_U32_e64 0, %0, %3, implicit %exec
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24
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25 ...
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26
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27 # GCN-LABEL: name: subb{{$}}
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28 # GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec
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29
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30 ---
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31 name: subb
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32 tracksRegLiveness: true
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33 registers:
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34 - { id: 0, class: vgpr_32 }
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35 - { id: 1, class: vgpr_32 }
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36 - { id: 2, class: vgpr_32 }
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37 - { id: 3, class: sreg_64_xexec }
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38 - { id: 4, class: vgpr_32 }
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39 - { id: 5, class: sreg_64_xexec }
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40 body: |
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41 bb.0:
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42
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43 %0 = IMPLICIT_DEF
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44 %1 = IMPLICIT_DEF
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45 %2 = IMPLICIT_DEF
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46 %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
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47 %4, %5 = V_SUBB_U32_e64 %0, 0, %3, implicit %exec
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48
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49 ...
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50
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51 # GCN-LABEL: name: addc{{$}}
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52 # GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
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53
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54 ---
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55 name: addc
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56 tracksRegLiveness: true
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57 registers:
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58 - { id: 0, class: vgpr_32 }
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59 - { id: 1, class: vgpr_32 }
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60 - { id: 2, class: vgpr_32 }
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61 - { id: 3, class: sreg_64_xexec }
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62 - { id: 4, class: vgpr_32 }
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63 - { id: 5, class: sreg_64_xexec }
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64 body: |
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65 bb.0:
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66
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67 %0 = IMPLICIT_DEF
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68 %1 = IMPLICIT_DEF
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69 %2 = IMPLICIT_DEF
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70 %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
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71 %4, %5 = V_ADDC_U32_e64 0, %0, %3, implicit %exec
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73 ...
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74
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75 # GCN-LABEL: name: addc2{{$}}
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76 # GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
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77
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78 ---
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79 name: addc2
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80 tracksRegLiveness: true
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81 registers:
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82 - { id: 0, class: vgpr_32 }
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83 - { id: 1, class: vgpr_32 }
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84 - { id: 2, class: vgpr_32 }
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85 - { id: 3, class: sreg_64_xexec }
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86 - { id: 4, class: vgpr_32 }
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87 - { id: 5, class: sreg_64_xexec }
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88 body: |
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89 bb.0:
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90
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91 %0 = IMPLICIT_DEF
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92 %1 = IMPLICIT_DEF
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93 %2 = IMPLICIT_DEF
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94 %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
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95 %4, %5 = V_ADDC_U32_e64 %0, 0, %3, implicit %exec
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96
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97 ...