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120
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1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
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2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
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121
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3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOVCCZ-BUG %s
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120
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4
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5 ; GCN-FUNC: {{^}}vccz_workaround:
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6 ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0
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7 ; GCN: v_cmp_neq_f32_e64 vcc, s{{[0-9]+}}, 0{{$}}
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121
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8 ; VCCZ-BUG: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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120
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9 ; VCCZ-BUG: s_mov_b64 vcc, vcc
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10 ; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc
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11 ; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]]
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12 ; GCN: buffer_store_dword
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13 ; GCN: [[EXIT]]:
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14 ; GCN: s_endpgm
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121
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15 define amdgpu_kernel void @vccz_workaround(i32 addrspace(2)* %in, i32 addrspace(1)* %out, float %cond) {
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120
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16 entry:
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17 %cnd = fcmp oeq float 0.0, %cond
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18 %sgpr = load volatile i32, i32 addrspace(2)* %in
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19 br i1 %cnd, label %if, label %endif
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20
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21 if:
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22 store i32 %sgpr, i32 addrspace(1)* %out
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23 br label %endif
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24
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25 endif:
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26 ret void
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27 }
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28
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29 ; GCN-FUNC: {{^}}vccz_noworkaround:
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30 ; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}}
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31 ; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]]
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32 ; GCN: buffer_store_dword
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33 ; GCN: [[EXIT]]:
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34 ; GCN: s_endpgm
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121
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35 define amdgpu_kernel void @vccz_noworkaround(float addrspace(1)* %in, float addrspace(1)* %out) {
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120
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36 entry:
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37 %vgpr = load volatile float, float addrspace(1)* %in
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38 %cnd = fcmp oeq float 0.0, %vgpr
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39 br i1 %cnd, label %if, label %endif
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40
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41 if:
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42 store float %vgpr, float addrspace(1)* %out
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43 br label %endif
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44
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45 endif:
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46 ret void
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47 }
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