annotate test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll @ 128:c347d3398279 default tip

fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
1 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=TONGA %s
100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
2
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
3 ; On Tonga and Iceland, limited SGPR availability means care must be taken to
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
4 ; allocate scratch registers correctly. Check that this test compiles without
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
5 ; error.
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
6 ; TONGA-LABEL: test
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
7 define amdgpu_kernel void @test(<256 x i32> addrspace(1)* %out, <256 x i32> addrspace(1)* %in) {
100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
8 entry:
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
9 %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
10 %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo)
100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
11 %aptr = getelementptr <256 x i32>, <256 x i32> addrspace(1)* %in, i32 %tid
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
12 %a = load <256 x i32>, <256 x i32> addrspace(1)* %aptr
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
13 call void asm sideeffect "", "~{memory}" ()
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
14 %outptr = getelementptr <256 x i32>, <256 x i32> addrspace(1)* %in, i32 %tid
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
15 store <256 x i32> %a, <256 x i32> addrspace(1)* %outptr
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
16
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
17 ; mark 128-bit SGPR registers as used so they are unavailable for the
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
18 ; scratch resource descriptor
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
19 call void asm sideeffect "", "~{SGPR4},~{SGPR8},~{SGPR12},~{SGPR16},~{SGPR20},~{SGPR24},~{SGPR28}" ()
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
20 call void asm sideeffect "", "~{SGPR32},~{SGPR36},~{SGPR40},~{SGPR44},~{SGPR48},~{SGPR52},~{SGPR56}" ()
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
21 call void asm sideeffect "", "~{SGPR60},~{SGPR64},~{SGPR68}" ()
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
22 ret void
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
23 }
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents:
diff changeset
24
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
25 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
26 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
27
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
28 attributes #0 = { nounwind readnone }