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121
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1 # RUN: llc -o - %s -mtriple=amdgcn-- -mcpu=fiji -verify-machineinstrs -run-pass=greedy,virtregrewriter | FileCheck %s
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2 --- |
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3 define amdgpu_kernel void @func0() #0 { ret void }
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4 define amdgpu_kernel void @func1() #0 { ret void }
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5 define amdgpu_kernel void @splitHoist() #0 { ret void }
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6
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7 attributes #0 = { "amdgpu-num-sgpr"="12" }
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8 ...
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9 ---
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10 # Make sure we only get a single spill+reload even if liverange splitting
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11 # created a sequence of multiple copy instructions.
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12 # CHECK-LABEL: name: func0
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13 # CHECK: SI_SPILL_S128_SAVE
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14 # CHECK-NOT: SI_SPILL_S128_SAVE
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15 # CHECK: S_NOP 0
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16 # CHECK: SI_SPILL_S128_RESTORE
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17 # CHECK-NOT: SI_SPILL_S128_RESTORE
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18 name: func0
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19 body: |
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20 bb.0:
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21 S_NOP 0, implicit-def undef %0.sub0 : sreg_128
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22 S_NOP 0, implicit-def %0.sub3 : sreg_128
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23
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24 ; Clobber registers
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25 S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
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26
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27 S_NOP 0, implicit %0.sub0
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28 S_NOP 0, implicit %0.sub3
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29 S_NOP 0, implicit %0.sub0
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30 S_NOP 0, implicit %0.sub3
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31 ...
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32 ---
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33 # LiveRange splitting should split this into 2 intervals with the second getting
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34 # allocated to sgpr0_sgpr1 and the first to something else so we see two copies
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35 # in between for the two subregisters that are alive.
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36 # CHECK-LABEL: name: func1
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37 # CHECK: [[REG0:%sgpr[0-9]+]] = COPY %sgpr0
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38 # CHECK: [[REG1:%sgpr[0-9]+]] = COPY %sgpr2
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39 # CHECK: S_NOP 0
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40 # CHECK: S_NOP 0, implicit [[REG0]]
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41 # CHECK: S_NOP 0, implicit [[REG1]]
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42 # CHECK: %sgpr0 = COPY [[REG0]]
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43 # CHECK: %sgpr2 = COPY [[REG1]]
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44 # CHECK: S_NOP
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45 # CHECK: S_NOP 0, implicit %sgpr0
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46 # CHECK: S_NOP 0, implicit %sgpr2
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47 name: func1
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48 tracksRegLiveness: true
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49 body: |
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50 bb.0:
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51 liveins: %sgpr0, %sgpr1, %sgpr2
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52 undef %0.sub0 : sreg_128 = COPY %sgpr0
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53 %0.sub2 = COPY %sgpr2
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54
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55 S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1
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56
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57 S_NOP 0, implicit %0.sub0
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58 S_NOP 0, implicit %0.sub2
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59
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60 ; Clobber everything but sgpr0-sgpr3
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61 S_NOP 0, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11, implicit-def dead %sgpr12, implicit-def dead %sgpr13, implicit-def dead %sgpr14, implicit-def dead %sgpr15, implicit-def dead %vcc_lo, implicit-def dead %vcc_hi
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62
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63 S_NOP 0, implicit %0.sub0
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64 S_NOP 0, implicit %0.sub2
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65 ...
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66 ---
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67 # Check that copy hoisting out of loops works. This mainly should not crash the
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68 # compiler when it hoists a subreg copy sequence.
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69 # CHECK-LABEL: name: splitHoist
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70 # CHECK: S_NOP 0, implicit-def %sgpr0
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71 # CHECK: S_NOP 0, implicit-def %sgpr3
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72 # CHECK-NEXT: SI_SPILL_S128_SAVE
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73 name: splitHoist
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74 tracksRegLiveness: true
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75 body: |
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76 bb.0:
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77 successors: %bb.1, %bb.2
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78 S_NOP 0, implicit-def undef %0.sub0 : sreg_128
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79 S_NOP 0, implicit-def %0.sub3 : sreg_128
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80
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81 S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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82 S_BRANCH %bb.2
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83
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84 bb.1:
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85 successors: %bb.1, %bb.3
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86 S_NOP 0, implicit %0.sub0
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87
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88 ; Clobber registers
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89 S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
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90
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91 S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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92 S_BRANCH %bb.3
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93
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94 bb.2:
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95 successors: %bb.3
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96 ; Clobber registers
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97 S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
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98 S_BRANCH %bb.3
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99
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100 bb.3:
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101 S_NOP 0, implicit %0.sub0
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102 S_NOP 0, implicit %0.sub3
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103 S_NOP 0, implicit %0.sub0
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104 S_NOP 0, implicit %0.sub3
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105 ...
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