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120
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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2 ; We may have subregister live ranges that are undefined on some paths. The
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3 ; verifier should not complain about this.
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4
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5
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6 ; CHECK-LABEL: {{^}}func:
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121
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7 define amdgpu_kernel void @func() #0 {
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120
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8 B0:
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9 br i1 undef, label %B1, label %B2
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10
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11 B1:
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12 br label %B2
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13
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14 B2:
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15 %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float undef>, %B0 ]
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16 br i1 undef, label %B30.1, label %B30.2
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17
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18 B30.1:
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19 %sub = fsub <4 x float> %v0, undef
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20 br label %B30.2
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21
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22 B30.2:
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23 %v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v0, %B2 ]
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24 %ve0 = extractelement <4 x float> %v3, i32 0
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25 store float %ve0, float addrspace(3)* undef, align 4
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26 ret void
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27 }
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28
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29 ; FIXME: Extra undef subregister copy should be removed before
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30 ; overwritten with defined copy
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31 ; CHECK-LABEL: {{^}}valley_partially_undef_copy:
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32 define amdgpu_ps float @valley_partially_undef_copy() #0 {
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33 bb:
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34 %tmp = load volatile i32, i32 addrspace(1)* undef, align 4
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35 %tmp1 = load volatile i32, i32 addrspace(1)* undef, align 4
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36 %tmp2 = insertelement <4 x i32> undef, i32 %tmp1, i32 0
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37 %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1
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121
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38 %tmp3.cast = bitcast <4 x i32> %tmp3 to <4 x float>
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39 %tmp4 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %tmp3.cast, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
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120
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40 %tmp5 = extractelement <4 x float> %tmp4, i32 0
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41 %tmp6 = fmul float %tmp5, undef
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42 %tmp7 = fadd float %tmp6, %tmp6
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43 %tmp8 = insertelement <4 x i32> %tmp2, i32 %tmp, i32 1
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44 store <4 x i32> %tmp8, <4 x i32> addrspace(1)* undef, align 16
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45 store float %tmp7, float addrspace(1)* undef, align 4
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46 br label %bb9
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47
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48 bb9: ; preds = %bb9, %bb
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49 %tmp10 = icmp eq i32 %tmp, 0
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50 br i1 %tmp10, label %bb9, label %bb11
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51
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52 bb11: ; preds = %bb9
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53 store <4 x i32> %tmp2, <4 x i32> addrspace(1)* undef, align 16
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54 ret float undef
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55 }
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56
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57 ; FIXME: Should be able to remove the undef copies
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58
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59 ; CHECK-LABEL: {{^}}partially_undef_copy:
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60 ; CHECK: v_mov_b32_e32 v5, 5
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61 ; CHECK: v_mov_b32_e32 v6, 6
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62
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63 ; CHECK: v_mov_b32_e32 v[[OUTPUT_LO:[0-9]+]], v5
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64
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65 ; Undef copy
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66 ; CHECK: v_mov_b32_e32 v1, v6
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67
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68 ; undef copy
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69 ; CHECK: v_mov_b32_e32 v2, v7
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70
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71 ; CHECK: v_mov_b32_e32 v[[OUTPUT_HI:[0-9]+]], v8
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72 ; CHECK: v_mov_b32_e32 v[[OUTPUT_LO]], v6
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73
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74 ; CHECK: buffer_store_dwordx4 v{{\[}}[[OUTPUT_LO]]:[[OUTPUT_HI]]{{\]}}
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121
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75 define amdgpu_kernel void @partially_undef_copy() #0 {
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76 %tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"()
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77 %tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"()
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120
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78
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79 %partially.undef.0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
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80 %partially.undef.1 = insertelement <4 x i32> %partially.undef.0, i32 %tmp1, i32 0
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81
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82 store volatile <4 x i32> %partially.undef.1, <4 x i32> addrspace(1)* undef, align 16
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121
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83 tail call void asm sideeffect "v_nop", "v={v[5:8]}"(<4 x i32> %partially.undef.0)
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120
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84 ret void
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85 }
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86
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121
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87 declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
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120
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88
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89 attributes #0 = { nounwind }
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121
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90 attributes #1 = { nounwind readonly }
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