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121
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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95
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3
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120
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4 declare i32 @llvm.amdgcn.workitem.id.x() #1
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5
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121
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6 ; GCN-LABEL: {{^}}v_cnd_nan_nosgpr:
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7 ; GCN: v_cmp_eq_u32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0
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8 ; GCN: v_cndmask_b32_e{{32|64}} v{{[0-9]}}, -1, v{{[0-9]+}}, [[COND]]
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9 ; GCN-DAG: v{{[0-9]}}
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10 ; All nan values are converted to 0xffffffff
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121
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11 ; GCN: s_endpgm
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12 define amdgpu_kernel void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 {
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120
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13 %idx = call i32 @llvm.amdgcn.workitem.id.x() #1
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14 %f.gep = getelementptr float, float addrspace(1)* %fptr, i32 %idx
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121
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15 %f = load float, float addrspace(1)* %f.gep
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16 %setcc = icmp ne i32 %c, 0
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17 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
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18 store float %select, float addrspace(1)* %out
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19 ret void
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20 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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21
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22
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23 ; This requires slightly trickier SGPR operand legalization since the
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24 ; single constant bus SGPR usage is the last operand, and it should
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25 ; never be moved.
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26
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121
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27 ; GCN-LABEL: {{^}}v_cnd_nan:
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28 ; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0
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29 ; GCN: v_cndmask_b32_e32 v{{[0-9]}}, -1, v{{[0-9]}}, vcc
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30 ; GCN-DAG: v{{[0-9]}}
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31 ; All nan values are converted to 0xffffffff
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121
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32 ; GCN: s_endpgm
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33 define amdgpu_kernel void @v_cnd_nan(float addrspace(1)* %out, i32 %c, float %f) #0 {
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34 %setcc = icmp ne i32 %c, 0
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35 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
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36 store float %select, float addrspace(1)* %out
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37 ret void
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38 }
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39
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121
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40 ; Test different compare and select operand types for optimal code
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41 ; shrinking.
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42 ; (select (cmp (sgprX, constant)), constant, sgprZ)
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43
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44 ; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k1_sgprZ_f32:
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45 ; GCN: s_load_dword [[X:s[0-9]+]]
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46 ; GCN: s_load_dword [[Z:s[0-9]+]]
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47 ; GCN-DAG: v_cmp_nlg_f32_e64 vcc, [[X]], 0
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48 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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49 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VZ]], vcc
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50 define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_sgprZ_f32(float addrspace(1)* %out, float %x, float %z) #0 {
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51 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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52 %tid.ext = sext i32 %tid to i64
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53 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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54 %setcc = fcmp one float %x, 0.0
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55 %select = select i1 %setcc, float 1.0, float %z
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56 store float %select, float addrspace(1)* %out.gep
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57 ret void
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58 }
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59
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60 ; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k1_sgprX_f32:
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61 ; GCN: s_load_dword [[X:s[0-9]+]]
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62 ; GCN-DAG: v_cmp_nlg_f32_e64 vcc, [[X]], 0
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63 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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64 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VZ]], vcc
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65 define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_sgprX_f32(float addrspace(1)* %out, float %x) #0 {
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66 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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67 %tid.ext = sext i32 %tid to i64
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68 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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69 %setcc = fcmp one float %x, 0.0
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70 %select = select i1 %setcc, float 1.0, float %x
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71 store float %select, float addrspace(1)* %out.gep
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72 ret void
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73 }
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74
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75 ; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k0_sgprZ_f32:
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76 ; GCN: s_load_dword [[X:s[0-9]+]]
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77 ; GCN-DAG: v_cmp_nlg_f32_e64 vcc, [[X]], 0
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78 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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79 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, [[VZ]], vcc
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80 define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_sgprZ_f32(float addrspace(1)* %out, float %x, float %z) #0 {
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81 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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82 %tid.ext = sext i32 %tid to i64
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83 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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84 %setcc = fcmp one float %x, 0.0
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85 %select = select i1 %setcc, float 0.0, float %z
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86 store float %select, float addrspace(1)* %out.gep
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87 ret void
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88 }
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89
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90 ; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k0_sgprX_f32:
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91 ; GCN: s_load_dword [[X:s[0-9]+]]
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92 ; GCN-DAG: v_cmp_nlg_f32_e64 vcc, [[X]], 0
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93 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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94 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, [[VZ]], vcc
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95 define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_sgprX_f32(float addrspace(1)* %out, float %x) #0 {
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96 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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97 %tid.ext = sext i32 %tid to i64
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98 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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99 %setcc = fcmp one float %x, 0.0
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100 %select = select i1 %setcc, float 0.0, float %x
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101 store float %select, float addrspace(1)* %out.gep
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102 ret void
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103 }
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104
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105 ; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k0_vgprZ_f32:
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106 ; GCN-DAG: s_load_dword [[X:s[0-9]+]]
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107 ; GCN-DAG: {{buffer|flat}}_load_dword [[Z:v[0-9]+]]
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108 ; GCN-DAG: v_cmp_nlg_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], [[X]], 0
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109 ; GCN: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, 0, [[Z]], [[COND]]
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110 define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_vgprZ_f32(float addrspace(1)* %out, float %x, float addrspace(1)* %z.ptr) #0 {
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111 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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112 %tid.ext = sext i32 %tid to i64
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113 %z.gep = getelementptr inbounds float, float addrspace(1)* %z.ptr, i64 %tid.ext
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114 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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115 %z = load float, float addrspace(1)* %z.gep
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116 %setcc = fcmp one float %x, 0.0
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117 %select = select i1 %setcc, float 0.0, float %z
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118 store float %select, float addrspace(1)* %out.gep
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119 ret void
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120 }
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121
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122 ; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k1_vgprZ_f32:
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123 ; GCN-DAG: {{buffer|flat}}_load_dword [[Z:v[0-9]+]]
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124 ; GCN-DAG: s_load_dword [[X:s[0-9]+]]
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125 ; GCN-DAG: v_cmp_nlg_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], [[X]], 0
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126 ; GCN: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, 1.0, [[Z]], [[COND]]
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127 define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_vgprZ_f32(float addrspace(1)* %out, float %x, float addrspace(1)* %z.ptr) #0 {
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128 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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129 %tid.ext = sext i32 %tid to i64
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130 %z.gep = getelementptr inbounds float, float addrspace(1)* %z.ptr, i64 %tid.ext
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131 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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132 %z = load float, float addrspace(1)* %z.gep
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133 %setcc = fcmp one float %x, 0.0
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134 %select = select i1 %setcc, float 1.0, float %z
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135 store float %select, float addrspace(1)* %out.gep
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136 ret void
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137 }
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138
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139 ; GCN-LABEL: {{^}}fcmp_vgprX_k0_select_k1_sgprZ_f32:
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140 ; GCN-DAG: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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141 ; GCN-DAG: s_load_dword [[Z:s[0-9]+]]
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142 ; GCN-DAG: v_cmp_ngt_f32_e32 vcc, 0, [[X]]
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143 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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144 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VZ]], vcc
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145 define amdgpu_kernel void @fcmp_vgprX_k0_select_k1_sgprZ_f32(float addrspace(1)* %out, float addrspace(1)* %x.ptr, float %z) #0 {
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146 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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147 %tid.ext = sext i32 %tid to i64
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148 %x.gep = getelementptr inbounds float, float addrspace(1)* %x.ptr, i64 %tid.ext
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149 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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150 %x = load float, float addrspace(1)* %x.gep
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151 %setcc = fcmp olt float %x, 0.0
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152 %select = select i1 %setcc, float 1.0, float %z
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153 store float %select, float addrspace(1)* %out.gep
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154 ret void
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155 }
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156
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157 ; GCN-LABEL: {{^}}fcmp_vgprX_k0_select_k1_vgprZ_f32:
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158 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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159 ; GCN: {{buffer|flat}}_load_dword [[Z:v[0-9]+]]
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160 ; GCN: v_cmp_le_f32_e32 vcc, 0, [[X]]
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161 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[Z]], vcc
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162 define amdgpu_kernel void @fcmp_vgprX_k0_select_k1_vgprZ_f32(float addrspace(1)* %out, float addrspace(1)* %x.ptr, float addrspace(1)* %z.ptr) #0 {
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163 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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164 %tid.ext = sext i32 %tid to i64
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165 %x.gep = getelementptr inbounds float, float addrspace(1)* %x.ptr, i64 %tid.ext
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166 %z.gep = getelementptr inbounds float, float addrspace(1)* %z.ptr, i64 %tid.ext
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167 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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168 %x = load volatile float, float addrspace(1)* %x.gep
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169 %z = load volatile float, float addrspace(1)* %z.gep
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170 %setcc = fcmp ult float %x, 0.0
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171 %select = select i1 %setcc, float 1.0, float %z
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172 store float %select, float addrspace(1)* %out.gep
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173 ret void
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174 }
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175
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176 ; GCN-LABEL: {{^}}icmp_vgprX_k0_select_k1_vgprZ_i32:
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177 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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178 ; GCN: {{buffer|flat}}_load_dword [[Z:v[0-9]+]]
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179 ; GCN: v_cmp_lt_i32_e32 vcc, -1, [[X]]
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180 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 2, [[Z]], vcc
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181 define amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %x.ptr, i32 addrspace(1)* %z.ptr) #0 {
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182 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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183 %tid.ext = sext i32 %tid to i64
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184 %x.gep = getelementptr inbounds i32, i32 addrspace(1)* %x.ptr, i64 %tid.ext
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185 %z.gep = getelementptr inbounds i32, i32 addrspace(1)* %z.ptr, i64 %tid.ext
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186 %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
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187 %x = load volatile i32, i32 addrspace(1)* %x.gep
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188 %z = load volatile i32, i32 addrspace(1)* %z.gep
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189 %setcc = icmp slt i32 %x, 0
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190 %select = select i1 %setcc, i32 2, i32 %z
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191 store i32 %select, i32 addrspace(1)* %out.gep
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192 ret void
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193 }
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194
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195 ; FIXME: Why does VI make the wrong regalloc choice?
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196 ; GCN-LABEL: {{^}}icmp_vgprX_k0_select_k1_vgprZ_i64:
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197 ; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[X_LO:[0-9]+]]:[[X_HI:[0-9]+]]{{\]}}
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198 ; GCN-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[Z_LO:[0-9]+]]:[[Z_HI:[0-9]+]]{{\]}}
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199 ; SI-DAG: v_cmp_lt_i64_e32 vcc, -1, v{{\[}}[[X_LO]]:[[X_HI]]{{\]}}
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200 ; SI-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v[[Z_HI]], vcc
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201 ; SI-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v[[Z_LO]], vcc
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202
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203 ; VI-DAG: v_cmp_lt_i64_e32 vcc, -1, v{{\[}}[[X_LO]]:[[X_HI]]{{\]}}
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204 ; VI-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v[[Z_HI]], vcc
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205 ; VI-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v[[Z_LO]], vcc
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206 define amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %x.ptr, i64 addrspace(1)* %z.ptr) #0 {
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207 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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208 %tid.ext = sext i32 %tid to i64
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209 %x.gep = getelementptr inbounds i64, i64 addrspace(1)* %x.ptr, i64 %tid.ext
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210 %z.gep = getelementptr inbounds i64, i64 addrspace(1)* %z.ptr, i64 %tid.ext
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211 %out.gep = getelementptr inbounds i64, i64 addrspace(1)* %out, i64 %tid.ext
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212 %x = load volatile i64, i64 addrspace(1)* %x.gep
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213 %z = load volatile i64, i64 addrspace(1)* %z.gep
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214 %setcc = icmp slt i64 %x, 0
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215 %select = select i1 %setcc, i64 2, i64 %z
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216 store i64 %select, i64 addrspace(1)* %out.gep
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217 ret void
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218 }
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219
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220 ; GCN-LABEL: {{^}}fcmp_vgprX_k0_select_vgprZ_k1_v4f32:
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221 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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222 ; GCN: {{buffer|flat}}_load_dwordx4
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223
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224 ; GCN: v_cmp_nge_f32_e32 vcc, 4.0, [[X]]
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225 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
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226 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}, vcc
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227 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, -0.5, v{{[0-9]+}}, vcc
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228 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}, vcc
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229 define amdgpu_kernel void @fcmp_vgprX_k0_select_vgprZ_k1_v4f32(<4 x float> addrspace(1)* %out, float addrspace(1)* %x.ptr, <4 x float> addrspace(1)* %z.ptr) #0 {
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230 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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231 %tid.ext = sext i32 %tid to i64
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232 %x.gep = getelementptr inbounds float, float addrspace(1)* %x.ptr, i64 %tid.ext
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233 %z.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %z.ptr, i64 %tid.ext
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234 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i64 %tid.ext
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235 %x = load volatile float, float addrspace(1)* %x.gep
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236 %z = load volatile <4 x float>, <4 x float> addrspace(1)* %z.gep
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237 %setcc = fcmp ugt float %x, 4.0
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238 %select = select i1 %setcc, <4 x float> %z, <4 x float> <float 1.0, float 2.0, float -0.5, float 4.0>
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239 store <4 x float> %select, <4 x float> addrspace(1)* %out.gep
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240 ret void
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241 }
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242
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243 ; GCN-LABEL: {{^}}fcmp_vgprX_k0_select_k1_vgprZ_v4f32:
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244 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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245 ; GCN: {{buffer|flat}}_load_dwordx4
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246
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247 ; GCN: v_cmp_ge_f32_e32 vcc, 4.0, [[X]]
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248 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
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249 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}, vcc
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250 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, -0.5, v{{[0-9]+}}, vcc
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251 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}, vcc
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252 define amdgpu_kernel void @fcmp_vgprX_k0_select_k1_vgprZ_v4f32(<4 x float> addrspace(1)* %out, float addrspace(1)* %x.ptr, <4 x float> addrspace(1)* %z.ptr) #0 {
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253 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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254 %tid.ext = sext i32 %tid to i64
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255 %x.gep = getelementptr inbounds float, float addrspace(1)* %x.ptr, i64 %tid.ext
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256 %z.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %z.ptr, i64 %tid.ext
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257 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i64 %tid.ext
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258 %x = load volatile float, float addrspace(1)* %x.gep
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259 %z = load volatile <4 x float>, <4 x float> addrspace(1)* %z.gep
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260 %setcc = fcmp ugt float %x, 4.0
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261 %select = select i1 %setcc, <4 x float> <float 1.0, float 2.0, float -0.5, float 4.0>, <4 x float> %z
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262 store <4 x float> %select, <4 x float> addrspace(1)* %out.gep
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263 ret void
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264 }
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265
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266 ; This must be swapped as a vector type before the condition has
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267 ; multiple uses.
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268
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269 ; GCN-LABEL: {{^}}fcmp_k0_vgprX_select_k1_vgprZ_v4f32:
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270 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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271 ; GCN: {{buffer|flat}}_load_dwordx4
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272
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273 ; GCN: v_cmp_le_f32_e32 vcc, 4.0, [[X]]
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274 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
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275 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}, vcc
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276 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, -0.5, v{{[0-9]+}}, vcc
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277 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}, vcc
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278 define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_v4f32(<4 x float> addrspace(1)* %out, float addrspace(1)* %x.ptr, <4 x float> addrspace(1)* %z.ptr) #0 {
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279 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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280 %tid.ext = sext i32 %tid to i64
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281 %x.gep = getelementptr inbounds float, float addrspace(1)* %x.ptr, i64 %tid.ext
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282 %z.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %z.ptr, i64 %tid.ext
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283 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i64 %tid.ext
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284 %x = load volatile float, float addrspace(1)* %x.gep
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285 %z = load volatile <4 x float>, <4 x float> addrspace(1)* %z.gep
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286 %setcc = fcmp ugt float 4.0, %x
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287 %select = select i1 %setcc, <4 x float> <float 1.0, float 2.0, float -0.5, float 4.0>, <4 x float> %z
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288 store <4 x float> %select, <4 x float> addrspace(1)* %out.gep
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289 ret void
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290 }
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291
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292 ; GCN-LABEL: {{^}}icmp_vgprX_k0_select_k1_vgprZ_i1:
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293 ; GCN: load_dword
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294 ; GCN: load_ubyte
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295 ; GCN-DAG: v_cmp_gt_i32_e32 vcc, 0, v
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296 ; DCN-DAG: v_and_b32_e32 v{{[0-9]+}}, 1,
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297 ; GCN-DAG: v_cmp_eq_u32_e64 s{{\[[0-9]+:[0-9]+\]}}, 1, v
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298 ; GCN-DAG: s_or_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc, s{{\[[0-9]+:[0-9]+\]}}
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299 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s
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300 ; GCN: store_byte
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301 define amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i1(i1 addrspace(1)* %out, i32 addrspace(1)* %x.ptr, i1 addrspace(1)* %z.ptr) #0 {
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302 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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303 %tid.ext = sext i32 %tid to i64
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304 %x.gep = getelementptr inbounds i32, i32 addrspace(1)* %x.ptr, i64 %tid.ext
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305 %z.gep = getelementptr inbounds i1, i1 addrspace(1)* %z.ptr, i64 %tid.ext
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306 %out.gep = getelementptr inbounds i1, i1 addrspace(1)* %out, i64 %tid.ext
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307 %x = load volatile i32, i32 addrspace(1)* %x.gep
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308 %z = load volatile i1, i1 addrspace(1)* %z.gep
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309 %setcc = icmp slt i32 %x, 0
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310 %select = select i1 %setcc, i1 true, i1 %z
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311 store i1 %select, i1 addrspace(1)* %out.gep
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312 ret void
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313 }
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314
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315 ; Different types compared vs. selected
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316 ; GCN-LABEL: {{^}}fcmp_vgprX_k0_selectf64_k1_vgprZ_f32:
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317 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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318 ; GCN: {{buffer|flat}}_load_dwordx2
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319
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320 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3ff00000
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321 ; GCN: v_cmp_le_f32_e32 vcc, 0, [[X]]
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322 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, [[K]], v{{[0-9]+}}, vcc
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323 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
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324 define amdgpu_kernel void @fcmp_vgprX_k0_selectf64_k1_vgprZ_f32(double addrspace(1)* %out, float addrspace(1)* %x.ptr, double addrspace(1)* %z.ptr) #0 {
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325 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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326 %tid.ext = sext i32 %tid to i64
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327 %x.gep = getelementptr inbounds float, float addrspace(1)* %x.ptr, i64 %tid.ext
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328 %z.gep = getelementptr inbounds double, double addrspace(1)* %z.ptr, i64 %tid.ext
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329 %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext
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330 %x = load volatile float, float addrspace(1)* %x.gep
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331 %z = load volatile double, double addrspace(1)* %z.gep
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332 %setcc = fcmp ult float %x, 0.0
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333 %select = select i1 %setcc, double 1.0, double %z
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334 store double %select, double addrspace(1)* %out.gep
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335 ret void
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336 }
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337
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338 ; Different types compared vs. selected
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339 ; GCN-LABEL: {{^}}fcmp_vgprX_k0_selecti64_k1_vgprZ_f32:
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340 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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341 ; GCN: {{buffer|flat}}_load_dwordx2
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342
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343 ; GCN: v_cmp_nlg_f32_e32 vcc, 0, [[X]]
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344 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 3, v{{[0-9]+}}, vcc
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345 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
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346 define amdgpu_kernel void @fcmp_vgprX_k0_selecti64_k1_vgprZ_f32(i64 addrspace(1)* %out, float addrspace(1)* %x.ptr, i64 addrspace(1)* %z.ptr) #0 {
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347 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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348 %tid.ext = sext i32 %tid to i64
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349 %x.gep = getelementptr inbounds float, float addrspace(1)* %x.ptr, i64 %tid.ext
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350 %z.gep = getelementptr inbounds i64, i64 addrspace(1)* %z.ptr, i64 %tid.ext
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351 %out.gep = getelementptr inbounds i64, i64 addrspace(1)* %out, i64 %tid.ext
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352 %x = load volatile float, float addrspace(1)* %x.gep
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353 %z = load volatile i64, i64 addrspace(1)* %z.gep
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354 %setcc = fcmp one float %x, 0.0
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355 %select = select i1 %setcc, i64 3, i64 %z
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356 store i64 %select, i64 addrspace(1)* %out.gep
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357 ret void
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358 }
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359
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360 ; Different types compared vs. selected
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361 ; GCN-LABEL: {{^}}icmp_vgprX_k0_selectf32_k1_vgprZ_i32:
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362 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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363 ; GCN: {{buffer|flat}}_load_dword [[Z:v[0-9]+]]
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364
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365 ; GCN: v_cmp_gt_u32_e32 vcc, 2, [[X]]
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366 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 4.0, [[Z]], vcc
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367 define amdgpu_kernel void @icmp_vgprX_k0_selectf32_k1_vgprZ_i32(float addrspace(1)* %out, i32 addrspace(1)* %x.ptr, float addrspace(1)* %z.ptr) #0 {
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368 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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369 %tid.ext = sext i32 %tid to i64
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370 %x.gep = getelementptr inbounds i32, i32 addrspace(1)* %x.ptr, i64 %tid.ext
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371 %z.gep = getelementptr inbounds float, float addrspace(1)* %z.ptr, i64 %tid.ext
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372 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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373 %x = load volatile i32, i32 addrspace(1)* %x.gep
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374 %z = load volatile float, float addrspace(1)* %z.gep
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375 %setcc = icmp ugt i32 %x, 1
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376 %select = select i1 %setcc, float 4.0, float %z
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377 store float %select, float addrspace(1)* %out.gep
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378 ret void
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379 }
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380
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381 ; FIXME: Should be able to handle multiple uses
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382
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383 ; GCN-LABEL: {{^}}fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2:
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384 ; GCN: {{buffer|flat}}_load_dword [[X:v[0-9]+]]
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385
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386 ; GCN: v_cmp_nle_f32_e32 vcc, 4.0, [[X]]
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387 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, -1.0, vcc
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388 ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, -2.0, vcc
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389 define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2(float addrspace(1)* %out, float addrspace(1)* %x.ptr, float addrspace(1)* %z.ptr) #0 {
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390 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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391 %tid.ext = sext i32 %tid to i64
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392 %x.gep = getelementptr inbounds float, float addrspace(1)* %x.ptr, i64 %tid.ext
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393 %z.gep = getelementptr inbounds float, float addrspace(1)* %z.ptr, i64 %tid.ext
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394 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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395 %x = load volatile float, float addrspace(1)* %x.gep
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396 %z = load volatile float, float addrspace(1)* %z.gep
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397 %setcc = fcmp ugt float 4.0, %x
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398 %select0 = select i1 %setcc, float -1.0, float %z
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399 %select1 = select i1 %setcc, float -2.0, float %z
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400 store volatile float %select0, float addrspace(1)* %out.gep
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401 store volatile float %select1, float addrspace(1)* %out.gep
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402 ret void
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403 }
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404
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95
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
405 attributes #0 = { nounwind }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406 attributes #1 = { nounwind readnone }
|
