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annotate test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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803732b1fca8 LLVM 5.0
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1 ; RUN: llc < %s -mattr=+neon
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2 ; PR4657
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4 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
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5 target triple = "armv7-apple-darwin9"
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7 define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind {
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8 entry:
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9 %v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
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10 %f_addr = alloca i32 ; <i32*> [#uses=2]
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11 %retval = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
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12 %0 = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
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13 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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14 store <4 x i32> %v, <4 x i32>* %v_addr
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15 store i32 %f, i32* %f_addr
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16 %1 = load <4 x i32>, <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1]
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17 %2 = load i32, i32* %f_addr, align 4 ; <i32> [#uses=1]
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18 %3 = insertelement <4 x i32> undef, i32 %2, i32 0 ; <<4 x i32>> [#uses=1]
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19 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>> [#uses=1]
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20 %5 = mul <4 x i32> %1, %4 ; <<4 x i32>> [#uses=1]
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21 store <4 x i32> %5, <4 x i32>* %0, align 16
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22 %6 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
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23 store <4 x i32> %6, <4 x i32>* %retval, align 16
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24 br label %return
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26 return: ; preds = %entry
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27 %retval1 = load <4 x i32>, <4 x i32>* %retval ; <<4 x i32>> [#uses=1]
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28 ret <4 x i32> %retval1
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29 }