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annotate test/CodeGen/ARM/bfx.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 1172e4bd9c6f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s
0
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2
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3 define i32 @sbfx1(i32 %a) {
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4 ; CHECK: sbfx1
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5 ; CHECK: sbfx r0, r0, #7, #11
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6 %t1 = lshr i32 %a, 7
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7 %t2 = trunc i32 %t1 to i11
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8 %t3 = sext i11 %t2 to i32
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9 ret i32 %t3
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10 }
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11
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12 define i32 @ubfx1(i32 %a) {
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13 ; CHECK: ubfx1
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14 ; CHECK: ubfx r0, r0, #7, #11
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15 %t1 = lshr i32 %a, 7
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16 %t2 = trunc i32 %t1 to i11
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17 %t3 = zext i11 %t2 to i32
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18 ret i32 %t3
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19 }
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20
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21 define i32 @ubfx2(i32 %a) {
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22 ; CHECK: ubfx2
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23 ; CHECK: ubfx r0, r0, #7, #11
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24 %t1 = lshr i32 %a, 7
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25 %t2 = and i32 %t1, 2047
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26 ret i32 %t2
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27 }
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28
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29 ; rdar://12870177
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30 define i32 @ubfx_opt(i32* nocapture %ctx, i32 %x) nounwind readonly ssp {
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31 entry:
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32 ; CHECK: ubfx_opt
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33 ; CHECK: lsr [[REG1:(lr|r[0-9]+)]], r1, #24
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34 ; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG1]], lsl #2]
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35 ; CHECK: ubfx [[REG2:(lr|r[0-9]+)]], r1, #16, #8
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36 ; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG2]], lsl #2]
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37 ; CHECK: ubfx [[REG3:(lr|r[0-9]+)]], r1, #8, #8
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38 ; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG3]], lsl #2]
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39 %and = lshr i32 %x, 8
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40 %shr = and i32 %and, 255
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41 %and1 = lshr i32 %x, 16
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42 %shr2 = and i32 %and1, 255
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43 %shr4 = lshr i32 %x, 24
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afa8332a0e37 LLVM 3.8
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44 %arrayidx = getelementptr inbounds i32, i32* %ctx, i32 %shr4
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45 %0 = load i32, i32* %arrayidx, align 4
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46 %arrayidx5 = getelementptr inbounds i32, i32* %ctx, i32 %shr2
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47 %1 = load i32, i32* %arrayidx5, align 4
0
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48 %add = add i32 %1, %0
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49 %arrayidx6 = getelementptr inbounds i32, i32* %ctx, i32 %shr
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50 %2 = load i32, i32* %arrayidx6, align 4
0
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51 %add7 = add i32 %add, %2
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52 ret i32 %add7
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53 }
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54
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55 define i32 @ubfx3(i32 %a) {
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56 ; CHECK: ubfx3
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57 ; CHECK: ubfx r0, r0, #11, #1
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58 %t1 = and i32 %a, 2048
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59 %t2 = lshr i32 %t1, 11
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60 ret i32 %t2
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61 }
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62
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63 define i32 @ubfx4(i32 %a) {
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64 ; CHECK: ubfx4
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65 ; CHECK: ubfx r0, r0, #7, #3
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66 %t1 = and i32 %a, 896
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67 %t2 = lshr i32 %t1, 7
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68 ret i32 %t2
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69 }