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annotate test/CodeGen/ARM/fabs-neon.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 54457678186b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s
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2
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3 ; CHECK-LABEL: test:
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4 ; CHECK: vabs.f32 q0, q0
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5 define <4 x float> @test(<4 x float> %a) {
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6 %foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
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7 ret <4 x float> %foo
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8 }
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9 declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
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10
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11 ; CHECK-LABEL: test2:
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12 ; CHECK: vabs.f32 d0, d0
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13 define <2 x float> @test2(<2 x float> %a) {
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14 %foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
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15 ret <2 x float> %foo
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16 }
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17 declare <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
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54457678186b LLVM 3.6
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54457678186b LLVM 3.6
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19 ; No constant pool loads or vector ops are needed for the fabs of a
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20 ; bitcasted integer constant; we should just return integer constants
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21 ; that have the sign bits turned off.
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22 ;
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23 ; So instead of something like this:
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24 ; mvn r0, #0
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25 ; mov r1, #0
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26 ; vmov d16, r1, r0
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27 ; vabs.f32 d16, d16
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28 ; vmov r0, r1, d16
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29 ; bx lr
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30 ;
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31 ; We should generate:
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32 ; mov r0, #0
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33 ; mvn r1, #-2147483648
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34 ; bx lr
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35
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36 define i64 @fabs_v2f32_1() {
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37 ; CHECK-LABEL: fabs_v2f32_1:
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38 ; CHECK: mvn r1, #-2147483648
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39 ; CHECK: bx lr
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40 ; CHECK-NOT: vabs
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41 %bitcast = bitcast i64 18446744069414584320 to <2 x float> ; 0xFFFF_FFFF_0000_0000
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42 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast)
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43 %ret = bitcast <2 x float> %fabs to i64
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44 ret i64 %ret
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45 }
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46
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47 define i64 @fabs_v2f32_2() {
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48 ; CHECK-LABEL: fabs_v2f32_2:
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49 ; CHECK: mvn r0, #-2147483648
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50 ; CHECK: bx lr
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51 ; CHECK-NOT: vabs
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52 %bitcast = bitcast i64 4294967295 to <2 x float> ; 0x0000_0000_FFFF_FFFF
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53 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast)
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54 %ret = bitcast <2 x float> %fabs to i64
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55 ret i64 %ret
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56 }