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annotate test/CodeGen/ARM/fast-isel-load-store-verify.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents afa8332a0e37
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL
afa8332a0e37 LLVM 3.8
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parents: 0
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2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL
0
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3
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4 ; FIXME Add tests for thumbv7, they currently fail MI verification because
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5 ; of a mismatch in register classes in uses.
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6
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7 ; This test verifies that load/store instructions are properly generated,
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8 ; and that they pass MI verification (wasn't the case until 2013-06-08).
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9
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10 @a = global i8 1, align 1
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11 @b = global i16 2, align 2
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12 @c = global i32 4, align 4
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13
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14 ; ldr
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15
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16 define i8 @t1() nounwind uwtable ssp {
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17 ; ALL: @t1
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18 ; ALL: ldrb
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19 ; ALL: add
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20 %1 = load i8, i8* @a, align 1
0
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21 %2 = add nsw i8 %1, 1
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22 ret i8 %2
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23 }
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24
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25 define i16 @t2() nounwind uwtable ssp {
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26 ; ALL: @t2
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27 ; ALL: ldrh
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28 ; ALL: add
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29 %1 = load i16, i16* @b, align 2
0
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30 %2 = add nsw i16 %1, 1
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31 ret i16 %2
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32 }
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33
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34 define i32 @t3() nounwind uwtable ssp {
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35 ; ALL: @t3
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36 ; ALL: ldr
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37 ; ALL: add
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38 %1 = load i32, i32* @c, align 4
0
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39 %2 = add nsw i32 %1, 1
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40 ret i32 %2
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41 }
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42
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43 ; str
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44
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45 define void @t4(i8 %v) nounwind uwtable ssp {
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46 ; ALL: @t4
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47 ; ALL: add
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48 ; ALL: strb
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49 %1 = add nsw i8 %v, 1
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50 store i8 %1, i8* @a, align 1
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51 ret void
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52 }
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53
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54 define void @t5(i16 %v) nounwind uwtable ssp {
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55 ; ALL: @t5
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56 ; ALL: add
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57 ; ALL: strh
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58 %1 = add nsw i16 %v, 1
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59 store i16 %1, i16* @b, align 2
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60 ret void
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61 }
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62
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63 define void @t6(i32 %v) nounwind uwtable ssp {
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parents:
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64 ; ALL: @t6
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65 ; ALL: add
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66 ; ALL: str
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67 %1 = add nsw i32 %v, 1
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parents:
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68 store i32 %1, i32* @c, align 4
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69 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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70 }