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1 # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \
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2 # RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT
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3 # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \
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4 # RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9
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5 # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \
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6 # RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52
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7 # REQUIRES: asserts
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8 --- |
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9 ; ModuleID = 'foo.ll'
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10 source_filename = "foo.ll"
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11 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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12 target triple = "arm---eabi"
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13
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14 define i64 @foo(i16 signext %a, i16 signext %b) {
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15 entry:
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16 %d = mul nsw i16 %a, %a
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17 %e = mul nsw i16 %b, %b
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18 %f = add nuw nsw i16 %e, %d
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19 %c = zext i16 %f to i32
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20 %mul8 = mul nsw i32 %c, %c
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21 %mul9 = mul nsw i32 %mul8, %mul8
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22 %add10 = add nuw nsw i32 %mul9, %mul8
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23 %conv1130 = zext i32 %add10 to i64
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24 %mul12 = mul nuw nsw i64 %conv1130, %conv1130
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25 %mul13 = mul nsw i64 %mul12, %mul12
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26 %add14 = add nuw nsw i64 %mul13, %mul12
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27 ret i64 %add14
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28 }
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29
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30 # CHECK: ********** MI Scheduling **********
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31 # CHECK: SU(2): %vreg2<def> = SMULBB %vreg1, %vreg1, pred:14, pred:%noreg; GPR:%vreg2,%vreg1,%vreg1
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32 # CHECK_A9: Latency : 2
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33 # CHECK_SWIFT: Latency : 4
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34 # CHECK_R52: Latency : 4
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35 #
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36 # CHECK: SU(3): %vreg3<def> = SMLABB %vreg0, %vreg0, %vreg2, pred:14, pred:%noreg; GPRnopc:%vreg3,%vreg0,%vreg0 GPR:%vreg2
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37 # CHECK_A9: Latency : 2
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38 # CHECK_SWIFT: Latency : 4
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39 # CHECK_R52: Latency : 4
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40 #
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41 # CHECK: SU(4): %vreg4<def> = UXTH %vreg3, 0, pred:14, pred:%noreg; GPRnopc:%vreg4,%vreg3
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42 # CHECK_A9: Latency : 1
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43 # CHECK_SWIFT: Latency : 1
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44 # CHECK_R52: Latency : 3
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45 #
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46 # CHECK: SU(5): %vreg5<def> = MUL %vreg4, %vreg4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg5,%vreg4,%vreg4
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47 # CHECK_A9: Latency : 2
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48 # CHECK_SWIFT: Latency : 4
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49 # CHECK_R52: Latency : 4
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50 #
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51 # CHECK: SU(6): %vreg6<def> = MLA %vreg5, %vreg5, %vreg5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg6,%vreg5,%vreg5,%vreg5
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52 # CHECK_A9: Latency : 2
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53 # CHECK_SWIFT: Latency : 4
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54 # CHECK_R52: Latency : 4
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55 #
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56 # CHECK: SU(7): %vreg7<def>, %vreg8<def> = UMULL %vreg6, %vreg6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg7,%vreg8,%vreg6,%vreg6
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57 # CHECK_A9: Latency : 3
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58 # CHECK_SWIFT: Latency : 5
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59 # CHECK_R52: Latency : 4
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60 #
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61 # CHECK: SU(11): %vreg13<def,tied4>, %vreg14<def,tied5> = UMLAL %vreg6, %vreg6, %vreg13<tied0>, %vreg14<tied1>, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg13 GPRnopc:%vreg14,%vreg6,%vreg6
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62 # CHECK_SWIFT: Latency : 7
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63 # CHECK_A9: Latency : 3
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64 # CHECK_R52: Latency : 4
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65 # CHECK: ** ScheduleDAGMILive::schedule picking next node
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66 ...
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67 ---
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68 name: foo
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69 alignment: 2
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70 exposesReturnsTwice: false
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71 legalized: false
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72 regBankSelected: false
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73 selected: false
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74 tracksRegLiveness: true
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75 registers:
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76 - { id: 0, class: gprnopc }
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77 - { id: 1, class: gpr }
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78 - { id: 2, class: gpr }
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79 - { id: 3, class: gprnopc }
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80 - { id: 4, class: gprnopc }
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81 - { id: 5, class: gprnopc }
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82 - { id: 6, class: gprnopc }
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83 - { id: 7, class: gprnopc }
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84 - { id: 8, class: gprnopc }
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85 - { id: 9, class: gpr }
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86 - { id: 10, class: gprnopc }
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87 - { id: 11, class: gprnopc }
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88 - { id: 12, class: gprnopc }
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89 - { id: 13, class: gpr }
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90 - { id: 14, class: gprnopc }
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91 liveins:
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92 - { reg: '%r0', virtual-reg: '%0' }
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93 - { reg: '%r1', virtual-reg: '%1' }
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94 frameInfo:
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95 isFrameAddressTaken: false
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96 isReturnAddressTaken: false
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97 hasStackMap: false
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98 hasPatchPoint: false
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99 stackSize: 0
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100 offsetAdjustment: 0
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101 maxAlignment: 0
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102 adjustsStack: false
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103 hasCalls: false
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104 maxCallFrameSize: 0
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105 hasOpaqueSPAdjustment: false
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106 hasVAStart: false
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107 hasMustTailInVarArgFunc: false
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108 body: |
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109 bb.0.entry:
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110 liveins: %r0, %r1
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111
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112 %1 = COPY %r1
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113 %0 = COPY %r0
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114 %2 = SMULBB %1, %1, 14, _
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115 %3 = SMLABB %0, %0, %2, 14, _
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116 %4 = UXTH %3, 0, 14, _
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117 %5 = MUL %4, %4, 14, _, _
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118 %6 = MLA %5, %5, %5, 14, _, _
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119 %7, %8 = UMULL %6, %6, 14, _, _
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120 %13, %10 = UMULL %7, %7, 14, _, _
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121 %11 = MLA %7, %8, %10, 14, _, _
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122 %14 = MLA %7, %8, %11, 14, _, _
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123 %13, %14 = UMLAL %6, %6, %13, %14, 14, _, _
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124 %r0 = COPY %13
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125 %r1 = COPY %14
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126 BX_RET 14, _, implicit %r0, implicit %r1
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127
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128 ...
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