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annotate test/CodeGen/Hexagon/block-addr.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; RUN: llc -march=hexagon < %s | FileCheck %s
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2
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3 ; CHECK-DAG: r[[REG:[0-9]+]] = memw(r{{[0-9]+<<#[0-9]+}}+##.LJTI{{.*}})
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4 ; CHECK-DAG: jumpr r[[REG]]
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6 define void @main() #0 {
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7 entry:
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8 %ret = alloca i32, align 4
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9 br label %while.body
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11 while.body:
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12 %ret.0.load17 = load volatile i32, i32* %ret, align 4
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13 switch i32 %ret.0.load17, label %label6 [
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14 i32 0, label %label0
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15 i32 1, label %label1
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16 i32 2, label %label2
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17 i32 3, label %label3
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18 i32 4, label %label4
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19 i32 5, label %label5
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20 ]
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21
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22 label0:
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23 %ret.0.load18 = load volatile i32, i32* %ret, align 4
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24 %inc = add nsw i32 %ret.0.load18, 1
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25 store volatile i32 %inc, i32* %ret, align 4
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26 br label %while.body
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28 label1:
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29 %ret.0.load19 = load volatile i32, i32* %ret, align 4
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30 %inc2 = add nsw i32 %ret.0.load19, 1
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31 store volatile i32 %inc2, i32* %ret, align 4
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32 br label %while.body
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34 label2:
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35 %ret.0.load20 = load volatile i32, i32* %ret, align 4
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36 %inc4 = add nsw i32 %ret.0.load20, 1
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37 store volatile i32 %inc4, i32* %ret, align 4
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38 br label %while.body
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40 label3:
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41 %ret.0.load21 = load volatile i32, i32* %ret, align 4
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42 %inc6 = add nsw i32 %ret.0.load21, 1
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43 store volatile i32 %inc6, i32* %ret, align 4
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44 br label %while.body
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46 label4:
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47 %ret.0.load22 = load volatile i32, i32* %ret, align 4
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48 %inc8 = add nsw i32 %ret.0.load22, 1
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49 store volatile i32 %inc8, i32* %ret, align 4
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50 br label %while.body
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52 label5:
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53 %ret.0.load23 = load volatile i32, i32* %ret, align 4
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54 %inc10 = add nsw i32 %ret.0.load23, 1
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55 store volatile i32 %inc10, i32* %ret, align 4
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56 br label %while.body
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57
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58 label6:
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59 store volatile i32 0, i32* %ret, align 4
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60 br label %while.body
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61 }
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63 attributes #0 = { noreturn nounwind "target-cpu"="hexagonv4" }