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annotate test/CodeGen/Hexagon/brev_ld.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
95
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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1 ; RUN: llc -march=hexagon < %s | FileCheck %s
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2 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
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3 ; Testing bitreverse load intrinsics:
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4 ; Q6_bitrev_load_update_D(inputLR, pDelay, nConvLength);
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5 ; Q6_bitrev_load_update_W(inputLR, pDelay, nConvLength);
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6 ; Q6_bitrev_load_update_H(inputLR, pDelay, nConvLength);
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7 ; Q6_bitrev_load_update_UH(inputLR, pDelay, nConvLength);
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8 ; Q6_bitrev_load_update_UB(inputLR, pDelay, nConvLength);
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9 ; Q6_bitrev_load_update_B(inputLR, pDelay, nConvLength);
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10 ; producing these instructions:
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11 ; r3:2 = memd(r0++m0:brev)
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12 ; r1 = memw(r0++m0:brev)
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13 ; r1 = memh(r0++m0:brev)
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14 ; r1 = memuh(r0++m0:brev)
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15 ; r1 = memub(r0++m0:brev)
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16 ; r1 = memb(r0++m0:brev)
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17
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18 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
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19 target triple = "hexagon"
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20
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21 define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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22 entry:
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23 %inputLR = alloca i64, align 8
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24 %conv = zext i16 %filtMemLen to i32
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25 %shr1 = lshr i32 %conv, 1
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26 %idxprom = sext i16 %filtMemIndex to i32
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27 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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28 %0 = bitcast i16* %arrayidx to i8*
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29 %1 = bitcast i64* %inputLR to i8*
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30 %sub = sub i32 13, %shr1
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31 %shl = shl i32 1, %sub
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32 ; CHECK: = memd(r{{[0-9]*}}++m{{[0-1]}}:brev)
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33 %2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl)
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34 %3 = bitcast i8* %1 to i64*
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35 %4 = load i64, i64* %3, align 8, !tbaa !0
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36 ret i64 %4
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37 }
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38
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39 declare i8* @llvm.hexagon.brev.ldd(i8*, i8*, i32) nounwind
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40
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41 define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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42 entry:
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43 %inputLR = alloca i32, align 4
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44 %conv = zext i16 %filtMemLen to i32
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45 %shr1 = lshr i32 %conv, 1
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46 %idxprom = sext i16 %filtMemIndex to i32
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47 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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48 %0 = bitcast i16* %arrayidx to i8*
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49 %1 = bitcast i32* %inputLR to i8*
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50 %sub = sub i32 14, %shr1
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51 %shl = shl i32 1, %sub
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52 ; CHECK: = memw(r{{[0-9]*}}++m{{[0-1]}}:brev)
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53 %2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl)
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54 %3 = bitcast i8* %1 to i32*
95
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55 %4 = load i32, i32* %3, align 4, !tbaa !2
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56 ret i32 %4
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57 }
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58
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59 declare i8* @llvm.hexagon.brev.ldw(i8*, i8*, i32) nounwind
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60
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61 define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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62 entry:
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63 %inputLR = alloca i16, align 2
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64 %conv = zext i16 %filtMemLen to i32
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65 %shr1 = lshr i32 %conv, 1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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66 %idxprom = sext i16 %filtMemIndex to i32
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67 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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68 %0 = bitcast i16* %arrayidx to i8*
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69 %1 = bitcast i16* %inputLR to i8*
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70 %sub = sub i32 15, %shr1
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71 %shl = shl i32 1, %sub
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72 ; CHECK: = memh(r{{[0-9]*}}++m0:brev)
95
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73 %2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl)
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74 %3 = bitcast i8* %1 to i16*
95
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75 %4 = load i16, i16* %3, align 2, !tbaa !3
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76 ret i16 %4
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77 }
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78
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79 declare i8* @llvm.hexagon.brev.ldh(i8*, i8*, i32) nounwind
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80
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81 define zeroext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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82 entry:
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83 %inputLR = alloca i16, align 2
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84 %conv = zext i16 %filtMemLen to i32
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85 %shr1 = lshr i32 %conv, 1
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86 %idxprom = sext i16 %filtMemIndex to i32
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87 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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88 %0 = bitcast i16* %arrayidx to i8*
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89 %1 = bitcast i16* %inputLR to i8*
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90 %sub = sub i32 15, %shr1
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91 %shl = shl i32 1, %sub
121
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92 ; CHECK: = memuh(r{{[0-9]*}}++m0:brev)
95
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93 %2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl)
120
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94 %3 = bitcast i8* %1 to i16*
95
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95 %4 = load i16, i16* %3, align 2, !tbaa !3
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96 ret i16 %4
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97 }
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98
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99 declare i8* @llvm.hexagon.brev.lduh(i8*, i8*, i32) nounwind
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100
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101 define zeroext i8 @foo4(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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102 entry:
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103 %inputLR = alloca i8, align 1
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104 %conv = zext i16 %filtMemLen to i32
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105 %shr1 = lshr i32 %conv, 1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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106 %idxprom = sext i16 %filtMemIndex to i32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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107 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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parents:
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108 %0 = bitcast i16* %arrayidx to i8*
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parents:
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109 %sub = sub nsw i32 16, %shr1
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110 %shl = shl i32 1, %sub
121
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111 ; CHECK: = memub(r{{[0-9]*}}++m{{[0-1]}}:brev)
95
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112 %1 = call i8* @llvm.hexagon.brev.ldub(i8* %0, i8* %inputLR, i32 %shl)
120
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113 %2 = load i8, i8* %inputLR, align 1, !tbaa !0
95
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114 ret i8 %2
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115 }
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116
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117 declare i8* @llvm.hexagon.brev.ldub(i8*, i8*, i32) nounwind
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parents:
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118
120
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119 define signext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
95
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120 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
121 %inputLR = alloca i8, align 1
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
122 %conv = zext i16 %filtMemLen to i32
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
123 %shr1 = lshr i32 %conv, 1
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
124 %idxprom = sext i16 %filtMemIndex to i32
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
125 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
126 %0 = bitcast i16* %arrayidx to i8*
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
127 %sub = sub nsw i32 16, %shr1
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
128 %shl = shl i32 1, %sub
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
129 ; CHECK: = memb(r{{[0-9]*}}++m{{[0-1]}}:brev)
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
130 %1 = call i8* @llvm.hexagon.brev.ldb(i8* %0, i8* %inputLR, i32 %shl)
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
131 %2 = load i8, i8* %inputLR, align 1, !tbaa !0
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 ret i8 %2
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
133 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
134
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
135 declare i8* @llvm.hexagon.brev.ldb(i8*, i8*, i32) nounwind
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
136
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 !0 = !{!"omnipotent char", !1}
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 !1 = !{!"Simple C/C++ TBAA"}
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 !2 = !{!"int", !0}
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 !3 = !{!"short", !0}