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120
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1 ; RUN: llc -march=hexagon < %s | FileCheck %s
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2
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3 ; After register allocation it is possible to have a spill of a register
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4 ; that is only partially defined. That in itself it fine, but creates a
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5 ; problem for double vector registers. Stores of such registers are pseudo
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6 ; instructions that are expanded into pairs of individual vector stores,
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7 ; and in case of a partially defined source, one of the stores may use
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8 ; an entirely undefined register.
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9 ;
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10 ; This testcase used to crash. Make sure we can handle it, and that we
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11 ; do generate a store for the defined part of W0:
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12
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13 ; CHECK-LABEL: fred:
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14 ; CHECK: v[[REG:[0-9]+]] = vsplat
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15 ; CHECK: vmem(r29+#6) = v[[REG]]
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16
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17
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18 target triple = "hexagon"
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19
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20 declare void @danny() local_unnamed_addr #0
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21 declare void @sammy() local_unnamed_addr #0
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22 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
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23 declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #1
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24 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
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25 declare <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32>, <32 x i32>) #1
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26 declare <32 x i32> @llvm.hexagon.V6.vlsrh.128B(<32 x i32>, i32) #1
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27 declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #1
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28
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29 define hidden void @fred() #2 {
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30 b0:
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31 %v1 = load i32, i32* null, align 4
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32 %v2 = icmp ult i64 0, 2147483648
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33 br i1 %v2, label %b3, label %b5
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34
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35 b3: ; preds = %b0
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36 %v4 = icmp sgt i32 0, -1
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37 br i1 %v4, label %b6, label %b5
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38
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39 b5: ; preds = %b3, %b0
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40 ret void
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41
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42 b6: ; preds = %b3
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43 tail call void @danny()
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44 br label %b7
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45
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46 b7: ; preds = %b21, %b6
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47 %v8 = icmp sgt i32 %v1, 0
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48 %v9 = select i1 %v8, i32 %v1, i32 0
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49 %v10 = select i1 false, i32 0, i32 %v9
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50 %v11 = icmp slt i32 %v10, 0
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51 %v12 = select i1 %v11, i32 %v10, i32 0
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52 %v13 = icmp slt i32 0, %v12
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53 br i1 %v13, label %b14, label %b18
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54
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55 b14: ; preds = %b16, %b7
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56 br i1 false, label %b15, label %b16
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57
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58 b15: ; preds = %b14
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59 br label %b16
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60
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61 b16: ; preds = %b15, %b14
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62 %v17 = icmp eq i32 0, %v12
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63 br i1 %v17, label %b18, label %b14
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64
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65 b18: ; preds = %b16, %b7
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66 tail call void @danny()
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67 %v19 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 524296) #0
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68 %v20 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v19, <32 x i32> %v19)
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69 br label %b22
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70
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71 b21: ; preds = %b22
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72 tail call void @sammy() #3
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73 br label %b7
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74
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75 b22: ; preds = %b22, %b18
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76 %v23 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> zeroinitializer, <64 x i32> %v20) #0
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77 %v24 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v23)
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78 %v25 = tail call <32 x i32> @llvm.hexagon.V6.vlsrh.128B(<32 x i32> %v24, i32 4) #0
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79 %v26 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> zeroinitializer, <32 x i32> %v25)
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80 %v27 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> zeroinitializer) #0
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81 %v28 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v26) #0
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82 %v29 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> %v28) #0
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83 store <32 x i32> %v27, <32 x i32>* null, align 128
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84 %v30 = add nsw i32 0, 128
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85 %v31 = getelementptr inbounds i8, i8* null, i32 %v30
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86 %v32 = bitcast i8* %v31 to <32 x i32>*
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87 store <32 x i32> %v29, <32 x i32>* %v32, align 128
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88 %v33 = icmp eq i32 0, 0
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89 br i1 %v33, label %b21, label %b22
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90 }
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91
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92 attributes #0 = { nounwind }
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93 attributes #1 = { nounwind readnone }
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121
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94 attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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120
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95 attributes #3 = { nobuiltin nounwind }
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