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annotate test/CodeGen/Hexagon/mul64-sext.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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121
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1 ; RUN: llc -march=hexagon < %s | FileCheck %s
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2
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3 target triple = "hexagon-unknown--elf"
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4
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5 ; CHECK-LABEL: mul_1
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6 ; CHECK: r1:0 = mpy(r2,r0)
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7 define i64 @mul_1(i64 %a0, i64 %a1) #0 {
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8 b2:
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9 %v3 = shl i64 %a0, 32
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10 %v4 = ashr exact i64 %v3, 32
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11 %v5 = shl i64 %a1, 32
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12 %v6 = ashr exact i64 %v5, 32
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13 %v7 = mul nsw i64 %v6, %v4
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14 ret i64 %v7
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15 }
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16
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17 ; CHECK-LABEL: mul_2
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18 ; CHECK: r0 = memb(r0+#0)
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19 ; CHECK: r1:0 = mpy(r2,r0)
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20 ; CHECK: jumpr r31
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21 define i64 @mul_2(i8* %a0, i64 %a1) #0 {
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22 b2:
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23 %v3 = load i8, i8* %a0
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24 %v4 = sext i8 %v3 to i64
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25 %v5 = shl i64 %a1, 32
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26 %v6 = ashr exact i64 %v5, 32
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27 %v7 = mul nsw i64 %v6, %v4
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28 ret i64 %v7
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29 }
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30
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31 ; CHECK-LABEL: mul_acc_1
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32 ; CHECK: r5:4 += mpy(r2,r0)
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33 ; CHECK: r1:0 = combine(r5,r4)
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34 ; CHECK: jumpr r31
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35 define i64 @mul_acc_1(i64 %a0, i64 %a1, i64 %a2) #0 {
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36 b3:
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37 %v4 = shl i64 %a0, 32
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38 %v5 = ashr exact i64 %v4, 32
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39 %v6 = shl i64 %a1, 32
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40 %v7 = ashr exact i64 %v6, 32
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41 %v8 = mul nsw i64 %v7, %v5
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42 %v9 = add i64 %a2, %v8
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43 ret i64 %v9
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44 }
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45
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46 ; CHECK-LABEL: mul_acc_2
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47 ; CHECK: r2 = memw(r2+#0)
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48 ; CHECK: r5:4 += mpy(r2,r0)
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49 ; CHECK: r1:0 = combine(r5,r4)
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50 ; CHECK: jumpr r31
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51 define i64 @mul_acc_2(i64 %a0, i32* %a1, i64 %a2) #0 {
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52 b3:
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53 %v4 = shl i64 %a0, 32
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54 %v5 = ashr exact i64 %v4, 32
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55 %v6 = load i32, i32* %a1
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56 %v7 = sext i32 %v6 to i64
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57 %v8 = mul nsw i64 %v7, %v5
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58 %v9 = add i64 %a2, %v8
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59 ret i64 %v9
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60 }
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61
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62 ; CHECK-LABEL: mul_nac_1
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63 ; CHECK: r5:4 -= mpy(r2,r0)
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64 ; CHECK: r1:0 = combine(r5,r4)
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65 ; CHECK: jumpr r31
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66 define i64 @mul_nac_1(i64 %a0, i64 %a1, i64 %a2) #0 {
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67 b3:
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68 %v4 = shl i64 %a0, 32
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69 %v5 = ashr exact i64 %v4, 32
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70 %v6 = shl i64 %a1, 32
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71 %v7 = ashr exact i64 %v6, 32
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72 %v8 = mul nsw i64 %v7, %v5
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73 %v9 = sub i64 %a2, %v8
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74 ret i64 %v9
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75 }
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76
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77 ; CHECK-LABEL: mul_nac_2
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78 ; CHECK: r0 = memw(r0+#0)
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79 ; CHECK: r5:4 -= mpy(r2,r0)
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80 ; CHECK: r1:0 = combine(r5,r4)
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81 ; CHECK: jumpr r31
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82 define i64 @mul_nac_2(i32* %a0, i64 %a1, i64 %a2) #0 {
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83 b3:
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84 %v4 = load i32, i32* %a0
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85 %v5 = sext i32 %v4 to i64
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86 %v6 = shl i64 %a1, 32
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87 %v7 = ashr exact i64 %v6, 32
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88 %v8 = mul nsw i64 %v7, %v5
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89 %v9 = sub i64 %a2, %v8
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90 ret i64 %v9
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91 }
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92
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93 attributes #0 = { nounwind }