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annotate test/CodeGen/Hexagon/rdf-cover-use.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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121
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1 ; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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2
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3 ; Check for sane output.
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4 ; CHECK: vmpyweh
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5
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6 target triple = "hexagon"
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7
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8 declare i32 @llvm.hexagon.S2.clb(i32) #0
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9 declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #0
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10 declare i32 @llvm.hexagon.S2.vrndpackwh(i64) #0
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11 declare i64 @llvm.hexagon.M2.mmpyl.s1(i64, i64) #0
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12
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13 define i64 @fred(i32 %a0, i32 %a1) local_unnamed_addr #1 {
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14 b2:
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15 br i1 undef, label %b15, label %b3
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16
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17 b3: ; preds = %b2
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18 %v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a1) #0
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19 %v5 = add nsw i32 %v4, -32
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20 %v6 = zext i32 %v5 to i64
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21 %v7 = shl nuw i64 %v6, 32
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22 %v8 = or i64 %v7, 0
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23 %v9 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 0)
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24 %v10 = tail call i32 @llvm.hexagon.S2.vrndpackwh(i64 %v8)
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25 %v11 = sext i32 %v9 to i64
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26 %v12 = sext i32 %v10 to i64
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27 %v13 = tail call i64 @llvm.hexagon.M2.mmpyl.s1(i64 %v11, i64 %v12)
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28 %v14 = and i64 %v13, 4294967295
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29 br label %b15
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30
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31 b15: ; preds = %b3, %b2
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32 %v16 = phi i64 [ %v14, %b3 ], [ 0, %b2 ]
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33 %v17 = or i64 0, %v16
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34 ret i64 %v17
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35 }
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36
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37 attributes #0 = { nounwind readnone }
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38 attributes #1 = { nounwind "target-cpu"="hexagonv55" }