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121
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1 ; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s
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120
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2 ; REQUIRES: asserts
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3
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4 target triple = "hexagon"
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5
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6 ; Function Attrs: nounwind
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7 define void @fred() #0 {
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8 entry:
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9 br label %for.body9.us
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10
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11 for.body9.us:
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12 %cmp10.us = icmp eq i32 0, undef
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13 %.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef
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14 %0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2)
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15 %1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %0)
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16 %2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1)
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17 %3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62)
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18 %4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3)
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19 store <16 x i32> %4, <16 x i32>* undef, align 64
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20 br i1 undef, label %for.body9.us, label %for.body43.us.preheader
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21
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22 for.body43.us.preheader: ; preds = %for.body9.us
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23 ret void
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24 }
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25
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26 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
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27 declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #1
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28 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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29 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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30 declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
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31
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32 attributes #0 = { nounwind }
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33 attributes #1 = { nounwind readnone }
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