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121
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1 ; Test load-and-trap instructions (LAT/LGAT)
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2 ;
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3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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4
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5 declare void @llvm.trap()
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6
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7 ; Check LAT with no displacement.
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8 define i32 @f1(i32 *%ptr) {
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9 ; CHECK-LABEL: f1:
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10 ; CHECK: lat %r2, 0(%r2)
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11 ; CHECK: br %r14
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12 entry:
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13 %val = load i32, i32 *%ptr
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14 %cmp = icmp eq i32 %val, 0
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15 br i1 %cmp, label %if.then, label %if.end
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16
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17 if.then: ; preds = %entry
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18 tail call void @llvm.trap()
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19 unreachable
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20
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21 if.end: ; preds = %entry
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22 ret i32 %val
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23 }
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24
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25 ; Check the high end of the LAT range.
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26 define i32 @f2(i32 *%src) {
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27 ; CHECK-LABEL: f2:
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28 ; CHECK: lat %r2, 524284(%r2)
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29 ; CHECK: br %r14
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30 %ptr = getelementptr i32, i32 *%src, i64 131071
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31 %val = load i32, i32 *%ptr
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32 %cmp = icmp eq i32 %val, 0
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33 br i1 %cmp, label %if.then, label %if.end
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34
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35 if.then: ; preds = %entry
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36 tail call void @llvm.trap()
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37 unreachable
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38
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39 if.end: ; preds = %entry
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40 ret i32 %val
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41 }
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42
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43 ; Check the next word up, which needs separate address logic.
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44 ; Other sequences besides this one would be OK.
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45 define i32 @f3(i32 *%src) {
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46 ; CHECK-LABEL: f3:
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47 ; CHECK: agfi %r2, 524288
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48 ; CHECK: lat %r2, 0(%r2)
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49 ; CHECK: br %r14
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50 %ptr = getelementptr i32, i32 *%src, i64 131072
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51 %val = load i32, i32 *%ptr
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52 %cmp = icmp eq i32 %val, 0
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53 br i1 %cmp, label %if.then, label %if.end
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54
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55 if.then: ; preds = %entry
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56 tail call void @llvm.trap()
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57 unreachable
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58
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59 if.end: ; preds = %entry
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60 ret i32 %val
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61 }
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62
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63 ; Check that LAT allows an index.
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64 define i32 @f4(i64 %src, i64 %index) {
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65 ; CHECK-LABEL: f4:
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66 ; CHECK: lat %r2, 524287(%r3,%r2)
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67 ; CHECK: br %r14
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68 %add1 = add i64 %src, %index
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69 %add2 = add i64 %add1, 524287
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70 %ptr = inttoptr i64 %add2 to i32 *
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71 %val = load i32, i32 *%ptr
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72 %cmp = icmp eq i32 %val, 0
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73 br i1 %cmp, label %if.then, label %if.end
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74
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75 if.then: ; preds = %entry
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76 tail call void @llvm.trap()
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77 unreachable
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78
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79 if.end: ; preds = %entry
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80 ret i32 %val
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81 }
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82
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83 ; Check LGAT with no displacement.
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84 define i64 @f5(i64 *%ptr) {
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85 ; CHECK-LABEL: f5:
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86 ; CHECK: lgat %r2, 0(%r2)
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87 ; CHECK: br %r14
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88 entry:
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89 %val = load i64, i64 *%ptr
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90 %cmp = icmp eq i64 %val, 0
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91 br i1 %cmp, label %if.then, label %if.end
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92
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93 if.then: ; preds = %entry
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94 tail call void @llvm.trap()
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95 unreachable
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96
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97 if.end: ; preds = %entry
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98 ret i64 %val
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99 }
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100
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101 ; Check the high end of the LGAT range.
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102 define i64 @f6(i64 *%src) {
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103 ; CHECK-LABEL: f6:
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104 ; CHECK: lgat %r2, 524280(%r2)
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105 ; CHECK: br %r14
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106 %ptr = getelementptr i64, i64 *%src, i64 65535
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107 %val = load i64, i64 *%ptr
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108 %cmp = icmp eq i64 %val, 0
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109 br i1 %cmp, label %if.then, label %if.end
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110
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111 if.then: ; preds = %entry
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112 tail call void @llvm.trap()
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113 unreachable
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114
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115 if.end: ; preds = %entry
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116 ret i64 %val
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117 }
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118
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119 ; Check the next word up, which needs separate address logic.
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120 ; Other sequences besides this one would be OK.
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121 define i64 @f7(i64 *%src) {
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122 ; CHECK-LABEL: f7:
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123 ; CHECK: agfi %r2, 524288
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124 ; CHECK: lgat %r2, 0(%r2)
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125 ; CHECK: br %r14
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126 %ptr = getelementptr i64, i64 *%src, i64 65536
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127 %val = load i64, i64 *%ptr
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128 %cmp = icmp eq i64 %val, 0
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129 br i1 %cmp, label %if.then, label %if.end
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130
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131 if.then: ; preds = %entry
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132 tail call void @llvm.trap()
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133 unreachable
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134
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135 if.end: ; preds = %entry
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136 ret i64 %val
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137 }
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138
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139 ; Check that LGAT allows an index.
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140 define i64 @f8(i64 %src, i64 %index) {
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141 ; CHECK-LABEL: f8:
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142 ; CHECK: lgat %r2, 524287(%r3,%r2)
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143 ; CHECK: br %r14
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144 %add1 = add i64 %src, %index
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145 %add2 = add i64 %add1, 524287
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146 %ptr = inttoptr i64 %add2 to i64 *
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147 %val = load i64, i64 *%ptr
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148 %cmp = icmp eq i64 %val, 0
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149 br i1 %cmp, label %if.then, label %if.end
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150
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151 if.then: ; preds = %entry
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152 tail call void @llvm.trap()
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153 unreachable
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154
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155 if.end: ; preds = %entry
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156 ret i64 %val
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157 }
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