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1 ; Test that vector compare / select combinations do not produce any
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2 ; unnecessary pack /unpack / shift instructions.
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3 ;
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4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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5 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefix=CHECK-Z14
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6
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7 define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4) {
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8 ; CHECK-LABEL: fun0:
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9 ; CHECK: # BB#0:
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10 ; CHECK-NEXT: vceqb %v0, %v24, %v26
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11 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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12 ; CHECK-NEXT: br %r14
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13 %cmp = icmp eq <2 x i8> %val1, %val2
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14 %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
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15 ret <2 x i8> %sel
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16 }
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17
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18 define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i16> %val3, <2 x i16> %val4) {
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19 ; CHECK-LABEL: fun1:
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20 ; CHECK: # BB#0:
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21 ; CHECK-NEXT: vceqb %v0, %v24, %v26
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22 ; CHECK-NEXT: vuphb %v0, %v0
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23 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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24 ; CHECK-NEXT: br %r14
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25 %cmp = icmp eq <2 x i8> %val1, %val2
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26 %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
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27 ret <2 x i16> %sel
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28 }
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29
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30 define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4) {
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31 ; CHECK-LABEL: fun2:
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32 ; CHECK: # BB#0:
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33 ; CHECK-NEXT: vceqb %v0, %v24, %v26
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34 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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35 ; CHECK-NEXT: br %r14
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36 %cmp = icmp eq <16 x i8> %val1, %val2
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37 %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
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38 ret <16 x i8> %sel
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39 }
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40
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41 define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4) {
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42 ; CHECK-LABEL: fun3:
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43 ; CHECK: # BB#0:
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44 ; CHECK-NEXT: vceqb %v0, %v24, %v26
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45 ; CHECK-DAG: vuphb [[REG0:%v[0-9]+]], %v0
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46 ; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
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47 ; CHECK-DAG: vuphb [[REG1]], [[REG1]]
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48 ; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG0]]
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49 ; CHECK-NEXT: vsel %v26, %v30, %v27, [[REG1]]
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50 ; CHECK-NEXT: br %r14
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51 %cmp = icmp eq <16 x i8> %val1, %val2
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52 %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
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53 ret <16 x i16> %sel
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54 }
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55
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56 define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4) {
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57 ; CHECK-LABEL: fun4:
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58 ; CHECK: # BB#0:
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59 ; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v26, %v30
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60 ; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v24, %v28
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61 ; CHECK-DAG: vsel %v24, %v25, %v29, [[REG1]]
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62 ; CHECK-DAG: vsel %v26, %v27, %v31, [[REG0]]
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63 ; CHECK-NEXT: br %r14
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64 %cmp = icmp eq <32 x i8> %val1, %val2
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65 %sel = select <32 x i1> %cmp, <32 x i8> %val3, <32 x i8> %val4
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66 ret <32 x i8> %sel
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67 }
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68
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69 define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4) {
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70 ; CHECK-LABEL: fun5:
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71 ; CHECK: # BB#0:
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72 ; CHECK-NEXT: vceqh %v0, %v24, %v26
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73 ; CHECK-NEXT: vpkh %v0, %v0, %v0
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74 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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75 ; CHECK-NEXT: br %r14
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76 %cmp = icmp eq <2 x i16> %val1, %val2
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77 %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
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78 ret <2 x i8> %sel
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79 }
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80
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81 define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4) {
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82 ; CHECK-LABEL: fun6:
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83 ; CHECK: # BB#0:
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84 ; CHECK-NEXT: vceqh %v0, %v24, %v26
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85 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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86 ; CHECK-NEXT: br %r14
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87 %cmp = icmp eq <2 x i16> %val1, %val2
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88 %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
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89 ret <2 x i16> %sel
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90 }
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91
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92 define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i32> %val4) {
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93 ; CHECK-LABEL: fun7:
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94 ; CHECK: # BB#0:
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95 ; CHECK-NEXT: vceqh %v0, %v24, %v26
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96 ; CHECK-NEXT: vuphh %v0, %v0
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97 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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98 ; CHECK-NEXT: br %r14
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99 %cmp = icmp eq <2 x i16> %val1, %val2
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100 %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
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101 ret <2 x i32> %sel
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102 }
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103
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104 define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i8> %val3, <8 x i8> %val4) {
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105 ; CHECK-LABEL: fun8:
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106 ; CHECK: # BB#0:
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107 ; CHECK-NEXT: vceqh %v0, %v24, %v26
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108 ; CHECK-NEXT: vpkh %v0, %v0, %v0
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109 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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110 ; CHECK-NEXT: br %r14
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111 %cmp = icmp eq <8 x i16> %val1, %val2
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112 %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
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113 ret <8 x i8> %sel
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114 }
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115
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116 define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4) {
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117 ; CHECK-LABEL: fun9:
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118 ; CHECK: # BB#0:
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119 ; CHECK-NEXT: vceqh %v0, %v24, %v26
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120 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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121 ; CHECK-NEXT: br %r14
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122 %cmp = icmp eq <8 x i16> %val1, %val2
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123 %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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124 ret <8 x i16> %sel
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125 }
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126
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127 define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x i32> %val4) {
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128 ; CHECK-LABEL: fun10:
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129 ; CHECK: # BB#0:
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130 ; CHECK-NEXT: vceqh %v0, %v24, %v26
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131 ; CHECK-DAG: vuphh [[REG0:%v[0-9]+]], %v0
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132 ; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
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133 ; CHECK-DAG: vuphh [[REG1]], [[REG1]]
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134 ; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG0]]
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135 ; CHECK-NEXT: vsel %v26, %v30, %v27, [[REG1]]
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136 ; CHECK-NEXT: br %r14
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137 %cmp = icmp eq <8 x i16> %val1, %val2
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138 %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
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139 ret <8 x i32> %sel
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140 }
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141
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142 define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i8> %val3, <16 x i8> %val4) {
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143 ; CHECK-LABEL: fun11:
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144 ; CHECK: # BB#0:
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145 ; CHECK-NEXT: vceqh %v0, %v26, %v30
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146 ; CHECK-NEXT: vceqh %v1, %v24, %v28
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147 ; CHECK-NEXT: vpkh %v0, %v1, %v0
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148 ; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
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149 ; CHECK-NEXT: br %r14
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150 %cmp = icmp eq <16 x i16> %val1, %val2
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151 %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
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152 ret <16 x i8> %sel
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153 }
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154
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155 define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4) {
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156 ; CHECK-LABEL: fun12:
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157 ; CHECK: # BB#0:
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158 ; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v26, %v30
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159 ; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v24, %v28
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160 ; CHECK-DAG: vsel %v24, %v25, %v29, [[REG1]]
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161 ; CHECK-DAG: vsel %v26, %v27, %v31, [[REG0]]
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162 ; CHECK-NEXT: br %r14
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163 %cmp = icmp eq <16 x i16> %val1, %val2
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164 %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
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165 ret <16 x i16> %sel
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166 }
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167
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168 define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i16> %val3, <2 x i16> %val4) {
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169 ; CHECK-LABEL: fun13:
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170 ; CHECK: # BB#0:
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171 ; CHECK-NEXT: vceqf %v0, %v24, %v26
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172 ; CHECK-NEXT: vpkf %v0, %v0, %v0
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173 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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174 ; CHECK-NEXT: br %r14
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175 %cmp = icmp eq <2 x i32> %val1, %val2
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176 %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
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177 ret <2 x i16> %sel
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178 }
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179
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180 define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4) {
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181 ; CHECK-LABEL: fun14:
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182 ; CHECK: # BB#0:
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183 ; CHECK-NEXT: vceqf %v0, %v24, %v26
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184 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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185 ; CHECK-NEXT: br %r14
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186 %cmp = icmp eq <2 x i32> %val1, %val2
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187 %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
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188 ret <2 x i32> %sel
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189 }
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190
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191 define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4) {
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192 ; CHECK-LABEL: fun15:
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193 ; CHECK: # BB#0:
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194 ; CHECK-NEXT: vceqf %v0, %v24, %v26
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195 ; CHECK-NEXT: vuphf %v0, %v0
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196 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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197 ; CHECK-NEXT: br %r14
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198 %cmp = icmp eq <2 x i32> %val1, %val2
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199 %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
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200 ret <2 x i64> %sel
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201 }
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202
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203 define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4) {
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204 ; CHECK-LABEL: fun16:
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205 ; CHECK: # BB#0:
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206 ; CHECK-NEXT: vceqf %v0, %v24, %v26
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207 ; CHECK-NEXT: vpkf %v0, %v0, %v0
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208 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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209 ; CHECK-NEXT: br %r14
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210 %cmp = icmp eq <4 x i32> %val1, %val2
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211 %sel = select <4 x i1> %cmp, <4 x i16> %val3, <4 x i16> %val4
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212 ret <4 x i16> %sel
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213 }
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214
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215 define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4) {
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216 ; CHECK-LABEL: fun17:
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217 ; CHECK: # BB#0:
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218 ; CHECK-NEXT: vceqf %v0, %v24, %v26
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219 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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220 ; CHECK-NEXT: br %r14
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221 %cmp = icmp eq <4 x i32> %val1, %val2
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222 %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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223 ret <4 x i32> %sel
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224 }
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225
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226 define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x i64> %val4) {
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227 ; CHECK-LABEL: fun18:
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228 ; CHECK: # BB#0:
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229 ; CHECK-NEXT: vceqf %v0, %v24, %v26
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230 ; CHECK-DAG: vuphf [[REG0:%v[0-9]+]], %v0
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231 ; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
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232 ; CHECK-DAG: vuphf [[REG1]], [[REG1]]
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233 ; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG0]]
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234 ; CHECK-NEXT: vsel %v26, %v30, %v27, [[REG1]]
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235 ; CHECK-NEXT: br %r14
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236 %cmp = icmp eq <4 x i32> %val1, %val2
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237 %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
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238 ret <4 x i64> %sel
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239 }
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240
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241 define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i16> %val3, <8 x i16> %val4) {
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242 ; CHECK-LABEL: fun19:
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243 ; CHECK: # BB#0:
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244 ; CHECK-NEXT: vceqf %v0, %v26, %v30
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245 ; CHECK-NEXT: vceqf %v1, %v24, %v28
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246 ; CHECK-NEXT: vpkf %v0, %v1, %v0
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247 ; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
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248 ; CHECK-NEXT: br %r14
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249 %cmp = icmp eq <8 x i32> %val1, %val2
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250 %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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251 ret <8 x i16> %sel
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252 }
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253
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254 define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4) {
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255 ; CHECK-LABEL: fun20:
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256 ; CHECK: # BB#0:
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257 ; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v26, %v30
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258 ; CHECK-DAG: vceqf [[REG1:%v[0-9]+]], %v24, %v28
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259 ; CHECK-DAG: vsel %v24, %v25, %v29, [[REG1]]
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260 ; CHECK-DAG: vsel %v26, %v27, %v31, [[REG0]]
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261 ; CHECK-NEXT: br %r14
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262 %cmp = icmp eq <8 x i32> %val1, %val2
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263 %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
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264 ret <8 x i32> %sel
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265 }
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266
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267 define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i32> %val3, <2 x i32> %val4) {
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268 ; CHECK-LABEL: fun21:
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269 ; CHECK: # BB#0:
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270 ; CHECK-NEXT: vceqg %v0, %v24, %v26
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271 ; CHECK-NEXT: vpkg %v0, %v0, %v0
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272 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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273 ; CHECK-NEXT: br %r14
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274 %cmp = icmp eq <2 x i64> %val1, %val2
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275 %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
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276 ret <2 x i32> %sel
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277 }
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278
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279 define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4) {
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280 ; CHECK-LABEL: fun22:
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281 ; CHECK: # BB#0:
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282 ; CHECK-NEXT: vceqg %v0, %v24, %v26
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283 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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284 ; CHECK-NEXT: br %r14
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285 %cmp = icmp eq <2 x i64> %val1, %val2
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286 %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
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287 ret <2 x i64> %sel
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288 }
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289
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290 define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4) {
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291 ; CHECK-LABEL: fun23:
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292 ; CHECK: # BB#0:
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293 ; CHECK-NEXT: vceqg %v0, %v26, %v30
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294 ; CHECK-NEXT: vceqg %v1, %v24, %v28
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295 ; CHECK-NEXT: vpkg %v0, %v1, %v0
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296 ; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
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297 ; CHECK-NEXT: br %r14
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298 %cmp = icmp eq <4 x i64> %val1, %val2
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299 %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
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300 ret <4 x i32> %sel
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301 }
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302
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303 define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4) {
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304 ; CHECK-LABEL: fun24:
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305 ; CHECK: # BB#0:
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306 ; CHECK-DAG: vceqg [[REG0:%v[0-9]+]], %v26, %v30
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307 ; CHECK-DAG: vceqg [[REG1:%v[0-9]+]], %v24, %v28
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308 ; CHECK-DAG: vsel %v24, %v25, %v29, [[REG1]]
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309 ; CHECK-DAG: vsel %v26, %v27, %v31, [[REG0]]
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310 ; CHECK-NEXT: br %r14
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311 %cmp = icmp eq <4 x i64> %val1, %val2
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312 %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
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313 ret <4 x i64> %sel
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314 }
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315
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316 define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x float> %val3, <2 x float> %val4) {
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317 ; CHECK-LABEL: fun25:
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318 ; CHECK: # BB#0:
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319 ; CHECK-NEXT: vmrlf %v0, %v26, %v26
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320 ; CHECK-NEXT: vmrlf %v1, %v24, %v24
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321 ; CHECK-NEXT: vldeb %v0, %v0
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322 ; CHECK-NEXT: vldeb %v1, %v1
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323 ; CHECK-NEXT: vfchdb %v0, %v1, %v0
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324 ; CHECK-NEXT: vmrhf %v1, %v26, %v26
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325 ; CHECK-NEXT: vmrhf %v2, %v24, %v24
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326 ; CHECK-NEXT: vldeb %v1, %v1
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327 ; CHECK-NEXT: vldeb %v2, %v2
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328 ; CHECK-NEXT: vfchdb %v1, %v2, %v1
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329 ; CHECK-NEXT: vpkg %v0, %v1, %v0
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330 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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331 ; CHECK-NEXT: br %r14
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332
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333 ; CHECK-Z14-LABEL: fun25:
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334 ; CHECK-Z14: # BB#0:
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335 ; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
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336 ; CHECK-Z14-NEXT: vsel %v24, %v28, %v30, %v0
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337 ; CHECK-Z14-NEXT: br %r14
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338
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339 %cmp = fcmp ogt <2 x float> %val1, %val2
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340 %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
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341 ret <2 x float> %sel
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342 }
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343
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344 define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4) {
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345 ; CHECK-LABEL: fun26:
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346 ; CHECK: # BB#0:
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347 ; CHECK-NEXT: vmrlf %v0, %v26, %v26
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348 ; CHECK-NEXT: vmrlf %v1, %v24, %v24
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349 ; CHECK-NEXT: vldeb %v0, %v0
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350 ; CHECK-NEXT: vldeb %v1, %v1
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351 ; CHECK-NEXT: vfchdb %v0, %v1, %v0
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352 ; CHECK-NEXT: vmrhf %v1, %v26, %v26
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353 ; CHECK-NEXT: vmrhf %v2, %v24, %v24
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354 ; CHECK-NEXT: vldeb %v1, %v1
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355 ; CHECK-NEXT: vldeb %v2, %v2
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356 ; CHECK-NEXT: vfchdb %v1, %v2, %v1
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357 ; CHECK-NEXT: vpkg %v0, %v1, %v0
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358 ; CHECK-NEXT: vuphf %v0, %v0
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359 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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360 ; CHECK-NEXT: br %r14
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361
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362 ; CHECK-Z14-LABEL: fun26:
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363 ; CHECK-Z14: # BB#0:
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364 ; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
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365 ; CHECK-Z14-NEXT: vuphf %v0, %v0
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366 ; CHECK-Z14-NEXT: vsel %v24, %v28, %v30, %v0
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367 ; CHECK-Z14-NEXT: br %r14
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368
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369 %cmp = fcmp ogt <2 x float> %val1, %val2
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370 %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
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|
371 ret <2 x double> %sel
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372 }
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373
|
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374 ; Test a widening select of floats.
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|
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375 define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2 x float> %val4) {
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|
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376 ; CHECK-LABEL: fun27:
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|
|
377 ; CHECK: # BB#0:
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|
378 ; CHECK-NEXT: vceqb %v0, %v24, %v26
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|
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379 ; CHECK-NEXT: vuphb %v0, %v0
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380 ; CHECK-NEXT: vuphh %v0, %v0
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|
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381 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
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|
|
382 ; CHECK-NEXT: br %r14
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383
|
|
|
384 %cmp = icmp eq <2 x i8> %val1, %val2
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|
|
385 %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
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|
|
386 ret <2 x float> %sel
|
|
|
387 }
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|
|
388
|
|
|
389 define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4) {
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|
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390 ; CHECK-LABEL: fun28:
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|
|
391 ; CHECK: # BB#0:
|
|
|
392 ; CHECK-NEXT: vmrlf %v0, %v26, %v26
|
|
|
393 ; CHECK-NEXT: vmrlf %v1, %v24, %v24
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|
|
394 ; CHECK-NEXT: vldeb %v0, %v0
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|
|
395 ; CHECK-NEXT: vldeb %v1, %v1
|
|
|
396 ; CHECK-NEXT: vfchdb %v0, %v1, %v0
|
|
|
397 ; CHECK-NEXT: vmrhf %v1, %v26, %v26
|
|
|
398 ; CHECK-NEXT: vmrhf %v2, %v24, %v24
|
|
|
399 ; CHECK-NEXT: vldeb %v1, %v1
|
|
|
400 ; CHECK-NEXT: vldeb %v2, %v2
|
|
|
401 ; CHECK-NEXT: vfchdb %v1, %v2, %v1
|
|
|
402 ; CHECK-NEXT: vpkg %v0, %v1, %v0
|
|
|
403 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
|
|
|
404 ; CHECK-NEXT: br %r14
|
|
|
405
|
|
|
406 ; CHECK-Z14-LABEL: fun28:
|
|
|
407 ; CHECK-Z14: # BB#0:
|
|
|
408 ; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
|
|
|
409 ; CHECK-Z14-NEXT: vsel %v24, %v28, %v30, %v0
|
|
|
410 ; CHECK-Z14-NEXT: br %r14
|
|
|
411
|
|
|
412 %cmp = fcmp ogt <4 x float> %val1, %val2
|
|
|
413 %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
|
|
|
414 ret <4 x float> %sel
|
|
|
415 }
|
|
|
416
|
|
|
417 define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x double> %val3, <4 x double> %val4) {
|
|
|
418 ; CHECK-LABEL: fun29:
|
|
|
419 ; CHECK: # BB#0:
|
|
|
420 ; CHECK-NEXT: vmrlf %v0, %v26, %v26
|
|
|
421 ; CHECK-NEXT: vmrlf %v1, %v24, %v24
|
|
|
422 ; CHECK-NEXT: vldeb %v0, %v0
|
|
|
423 ; CHECK-NEXT: vldeb %v1, %v1
|
|
|
424 ; CHECK-NEXT: vfchdb %v0, %v1, %v0
|
|
|
425 ; CHECK-NEXT: vmrhf %v1, %v26, %v26
|
|
|
426 ; CHECK-NEXT: vmrhf %v2, %v24, %v24
|
|
|
427 ; CHECK-NEXT: vldeb %v1, %v1
|
|
|
428 ; CHECK-NEXT: vldeb %v2, %v2
|
|
|
429 ; CHECK-NEXT: vfchdb %v1, %v2, %v1
|
|
|
430 ; CHECK-NEXT: vpkg [[REG0:%v[0-9]+]], %v1, %v0
|
|
|
431 ; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
|
|
|
432 ; CHECK-DAG: vuphf [[REG1]], [[REG1]]
|
|
|
433 ; CHECK-DAG: vuphf [[REG2:%v[0-9]+]], [[REG0]]
|
|
|
434 ; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG2]]
|
|
|
435 ; CHECK-NEXT: vsel %v26, %v30, %v27, [[REG1]]
|
|
|
436 ; CHECK-NEXT: br %r14
|
|
|
437
|
|
|
438 ; CHECK-Z14-LABEL: fun29:
|
|
|
439 ; CHECK-Z14: # BB#0:
|
|
|
440 ; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
|
|
|
441 ; CHECK-Z14-DAG: vuphf [[REG0:%v[0-9]+]], %v0
|
|
|
442 ; CHECK-Z14-DAG: vmrlg [[REG1:%v[0-9]+]], %v0, %v0
|
|
|
443 ; CHECK-Z14-DAG: vuphf [[REG1]], [[REG1]]
|
|
|
444 ; CHECK-Z14-NEXT: vsel %v24, %v28, %v25, [[REG0]]
|
|
|
445 ; CHECK-Z14-NEXT: vsel %v26, %v30, %v27, [[REG1]]
|
|
|
446 ; CHECK-Z14-NEXT: br %r14
|
|
|
447
|
|
|
448 %cmp = fcmp ogt <4 x float> %val1, %val2
|
|
|
449 %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
|
|
|
450 ret <4 x double> %sel
|
|
|
451 }
|
|
|
452
|
|
|
453 define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x float> %val3, <8 x float> %val4) {
|
|
|
454 ; CHECK-Z14-LABEL: fun30:
|
|
|
455 ; CHECK-Z14: # BB#0:
|
|
|
456 ; CHECK-Z14-DAG: vfchsb [[REG0:%v[0-9]+]], %v26, %v30
|
|
|
457 ; CHECK-Z14-DAG: vfchsb [[REG1:%v[0-9]+]], %v24, %v28
|
|
|
458 ; CHECK-Z14-DAG: vsel %v24, %v25, %v29, [[REG1]]
|
|
|
459 ; CHECK-Z14-DAG: vsel %v26, %v27, %v31, [[REG0]]
|
|
|
460 ; CHECK-Z14-NEXT: br %r14
|
|
|
461 %cmp = fcmp ogt <8 x float> %val1, %val2
|
|
|
462 %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
|
|
|
463 ret <8 x float> %sel
|
|
|
464 }
|
|
|
465
|
|
|
466 define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x float> %val3, <2 x float> %val4) {
|
|
|
467 ; CHECK-LABEL: fun31:
|
|
|
468 ; CHECK: # BB#0:
|
|
|
469 ; CHECK-NEXT: vfchdb %v0, %v24, %v26
|
|
|
470 ; CHECK-NEXT: vpkg %v0, %v0, %v0
|
|
|
471 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
|
|
|
472 ; CHECK-NEXT: br %r14
|
|
|
473
|
|
|
474 %cmp = fcmp ogt <2 x double> %val1, %val2
|
|
|
475 %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
|
|
|
476 ret <2 x float> %sel
|
|
|
477 }
|
|
|
478
|
|
|
479 define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4) {
|
|
|
480 ; CHECK-LABEL: fun32:
|
|
|
481 ; CHECK: # BB#0:
|
|
|
482 ; CHECK-NEXT: vfchdb %v0, %v24, %v26
|
|
|
483 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
|
|
|
484 ; CHECK-NEXT: br %r14
|
|
|
485 %cmp = fcmp ogt <2 x double> %val1, %val2
|
|
|
486 %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
|
|
|
487 ret <2 x double> %sel
|
|
|
488 }
|
|
|
489
|
|
|
490 define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4) {
|
|
|
491 ; CHECK-LABEL: fun33:
|
|
|
492 ; CHECK: # BB#0:
|
|
|
493 ; CHECK-NEXT: vfchdb %v0, %v26, %v30
|
|
|
494 ; CHECK-NEXT: vfchdb %v1, %v24, %v28
|
|
|
495 ; CHECK-NEXT: vpkg %v0, %v1, %v0
|
|
|
496 ; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
|
|
|
497 ; CHECK-NEXT: br %r14
|
|
|
498 %cmp = fcmp ogt <4 x double> %val1, %val2
|
|
|
499 %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
|
|
|
500 ret <4 x float> %sel
|
|
|
501 }
|
|
|
502
|
|
|
503 define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x double> %val3, <4 x double> %val4) {
|
|
|
504 ; CHECK-LABEL: fun34:
|
|
|
505 ; CHECK: # BB#0:
|
|
|
506 ; CHECK-DAG: vfchdb [[REG0:%v[0-9]+]], %v26, %v30
|
|
|
507 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v24, %v28
|
|
|
508 ; CHECK-DAG: vsel %v24, %v25, %v29, [[REG1]]
|
|
|
509 ; CHECK-DAG: vsel %v26, %v27, %v31, [[REG0]]
|
|
|
510 ; CHECK-NEXT: br %r14
|
|
|
511 %cmp = fcmp ogt <4 x double> %val1, %val2
|
|
|
512 %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
|
|
|
513 ret <4 x double> %sel
|
|
|
514 }
|
