120
|
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
121
|
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
3
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
4 define i32 @test1(float %x) {
|
120
|
5 ; CHECK-LABEL: test1:
|
|
6 ; CHECK: ## BB#0:
|
121
|
7 ; CHECK-NEXT: vmovd %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7e,0xc0]
|
120
|
8 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
9 %res = bitcast float %x to i32
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
10 ret i32 %res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
11 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
12
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
13 define <4 x i32> @test2(i32 %x) {
|
120
|
14 ; CHECK-LABEL: test2:
|
|
15 ; CHECK: ## BB#0:
|
121
|
16 ; CHECK-NEXT: vmovd %edi, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6e,0xc7]
|
120
|
17 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
18 %res = insertelement <4 x i32>undef, i32 %x, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
19 ret <4 x i32>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
20 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
21
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
22 define <2 x i64> @test3(i64 %x) {
|
120
|
23 ; CHECK-LABEL: test3:
|
|
24 ; CHECK: ## BB#0:
|
121
|
25 ; CHECK-NEXT: vmovq %rdi, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xf9,0x6e,0xc7]
|
120
|
26 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
27 %res = insertelement <2 x i64>undef, i64 %x, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
28 ret <2 x i64>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
29 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
30
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
31 define <4 x i32> @test4(i32* %x) {
|
120
|
32 ; CHECK-LABEL: test4:
|
|
33 ; CHECK: ## BB#0:
|
121
|
34 ; CHECK-NEXT: vmovss (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]
|
120
|
35 ; CHECK-NEXT: ## xmm0 = mem[0],zero,zero,zero
|
|
36 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
95
|
37 %y = load i32, i32* %x
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
38 %res = insertelement <4 x i32>undef, i32 %y, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
39 ret <4 x i32>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
40 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
41
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
42 define void @test5(float %x, float* %y) {
|
120
|
43 ; CHECK-LABEL: test5:
|
|
44 ; CHECK: ## BB#0:
|
121
|
45 ; CHECK-NEXT: vmovss %xmm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x11,0x07]
|
120
|
46 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
47 store float %x, float* %y, align 4
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
48 ret void
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
49 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
50
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
51 define void @test6(double %x, double* %y) {
|
120
|
52 ; CHECK-LABEL: test6:
|
|
53 ; CHECK: ## BB#0:
|
121
|
54 ; CHECK-NEXT: vmovsd %xmm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x11,0x07]
|
120
|
55 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
56 store double %x, double* %y, align 8
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
57 ret void
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
58 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
59
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
60 define float @test7(i32* %x) {
|
120
|
61 ; CHECK-LABEL: test7:
|
|
62 ; CHECK: ## BB#0:
|
121
|
63 ; CHECK-NEXT: vmovss (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]
|
120
|
64 ; CHECK-NEXT: ## xmm0 = mem[0],zero,zero,zero
|
|
65 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
95
|
66 %y = load i32, i32* %x
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
67 %res = bitcast i32 %y to float
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
68 ret float %res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
69 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
70
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
71 define i32 @test8(<4 x i32> %x) {
|
120
|
72 ; CHECK-LABEL: test8:
|
|
73 ; CHECK: ## BB#0:
|
121
|
74 ; CHECK-NEXT: vmovd %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7e,0xc0]
|
120
|
75 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
76 %res = extractelement <4 x i32> %x, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
77 ret i32 %res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
78 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
79
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
80 define i64 @test9(<2 x i64> %x) {
|
120
|
81 ; CHECK-LABEL: test9:
|
|
82 ; CHECK: ## BB#0:
|
121
|
83 ; CHECK-NEXT: vmovq %xmm0, %rax ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xf9,0x7e,0xc0]
|
120
|
84 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
85 %res = extractelement <2 x i64> %x, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
86 ret i64 %res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
87 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
88
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
89 define <4 x i32> @test10(i32* %x) {
|
120
|
90 ; CHECK-LABEL: test10:
|
|
91 ; CHECK: ## BB#0:
|
121
|
92 ; CHECK-NEXT: vmovss (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]
|
120
|
93 ; CHECK-NEXT: ## xmm0 = mem[0],zero,zero,zero
|
|
94 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
95
|
95 %y = load i32, i32* %x, align 4
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
96 %res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
97 ret <4 x i32>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
98 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
99
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
100 define <4 x float> @test11(float* %x) {
|
120
|
101 ; CHECK-LABEL: test11:
|
|
102 ; CHECK: ## BB#0:
|
121
|
103 ; CHECK-NEXT: vmovss (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]
|
120
|
104 ; CHECK-NEXT: ## xmm0 = mem[0],zero,zero,zero
|
|
105 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
95
|
106 %y = load float, float* %x, align 4
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
107 %res = insertelement <4 x float>zeroinitializer, float %y, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
108 ret <4 x float>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
109 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
110
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
111 define <2 x double> @test12(double* %x) {
|
120
|
112 ; CHECK-LABEL: test12:
|
|
113 ; CHECK: ## BB#0:
|
121
|
114 ; CHECK-NEXT: vmovsd (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x10,0x07]
|
120
|
115 ; CHECK-NEXT: ## xmm0 = mem[0],zero
|
|
116 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
95
|
117 %y = load double, double* %x, align 8
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
118 %res = insertelement <2 x double>zeroinitializer, double %y, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
119 ret <2 x double>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
120 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
121
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
122 define <2 x i64> @test13(i64 %x) {
|
120
|
123 ; CHECK-LABEL: test13:
|
|
124 ; CHECK: ## BB#0:
|
121
|
125 ; CHECK-NEXT: vmovq %rdi, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xf9,0x6e,0xc7]
|
120
|
126 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
127 %res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
128 ret <2 x i64>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
129 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
130
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
131 define <4 x i32> @test14(i32 %x) {
|
120
|
132 ; CHECK-LABEL: test14:
|
|
133 ; CHECK: ## BB#0:
|
121
|
134 ; CHECK-NEXT: vmovd %edi, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6e,0xc7]
|
120
|
135 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
136 %res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
137 ret <4 x i32>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
138 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
139
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
140 define <4 x i32> @test15(i32* %x) {
|
120
|
141 ; CHECK-LABEL: test15:
|
|
142 ; CHECK: ## BB#0:
|
121
|
143 ; CHECK-NEXT: vmovss (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]
|
120
|
144 ; CHECK-NEXT: ## xmm0 = mem[0],zero,zero,zero
|
|
145 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
95
|
146 %y = load i32, i32* %x, align 4
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
147 %res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
148 ret <4 x i32>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
149 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
150
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
151 define <16 x i32> @test16(i8 * %addr) {
|
120
|
152 ; CHECK-LABEL: test16:
|
|
153 ; CHECK: ## BB#0:
|
|
154 ; CHECK-NEXT: vmovups (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x07]
|
|
155 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
156 %vaddr = bitcast i8* %addr to <16 x i32>*
|
95
|
157 %res = load <16 x i32>, <16 x i32>* %vaddr, align 1
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
158 ret <16 x i32>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
159 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
160
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
161 define <16 x i32> @test17(i8 * %addr) {
|
120
|
162 ; CHECK-LABEL: test17:
|
|
163 ; CHECK: ## BB#0:
|
|
164 ; CHECK-NEXT: vmovaps (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]
|
|
165 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
166 %vaddr = bitcast i8* %addr to <16 x i32>*
|
95
|
167 %res = load <16 x i32>, <16 x i32>* %vaddr, align 64
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
168 ret <16 x i32>%res
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
169 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
170
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
171 define void @test18(i8 * %addr, <8 x i64> %data) {
|
120
|
172 ; CHECK-LABEL: test18:
|
|
173 ; CHECK: ## BB#0:
|
|
174 ; CHECK-NEXT: vmovaps %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x29,0x07]
|
|
175 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
176 %vaddr = bitcast i8* %addr to <8 x i64>*
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
177 store <8 x i64>%data, <8 x i64>* %vaddr, align 64
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
178 ret void
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
179 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
180
|
77
|
181 define void @test19(i8 * %addr, <16 x i32> %data) {
|
120
|
182 ; CHECK-LABEL: test19:
|
|
183 ; CHECK: ## BB#0:
|
|
184 ; CHECK-NEXT: vmovups %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x07]
|
|
185 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
186 %vaddr = bitcast i8* %addr to <16 x i32>*
|
|
187 store <16 x i32>%data, <16 x i32>* %vaddr, align 1
|
|
188 ret void
|
|
189 }
|
|
190
|
|
191 define void @test20(i8 * %addr, <16 x i32> %data) {
|
120
|
192 ; CHECK-LABEL: test20:
|
|
193 ; CHECK: ## BB#0:
|
|
194 ; CHECK-NEXT: vmovaps %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x29,0x07]
|
|
195 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
196 %vaddr = bitcast i8* %addr to <16 x i32>*
|
|
197 store <16 x i32>%data, <16 x i32>* %vaddr, align 64
|
|
198 ret void
|
|
199 }
|
|
200
|
|
201 define <8 x i64> @test21(i8 * %addr) {
|
120
|
202 ; CHECK-LABEL: test21:
|
|
203 ; CHECK: ## BB#0:
|
|
204 ; CHECK-NEXT: vmovaps (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]
|
|
205 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
206 %vaddr = bitcast i8* %addr to <8 x i64>*
|
95
|
207 %res = load <8 x i64>, <8 x i64>* %vaddr, align 64
|
77
|
208 ret <8 x i64>%res
|
|
209 }
|
|
210
|
|
211 define void @test22(i8 * %addr, <8 x i64> %data) {
|
120
|
212 ; CHECK-LABEL: test22:
|
|
213 ; CHECK: ## BB#0:
|
|
214 ; CHECK-NEXT: vmovups %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x07]
|
|
215 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
216 %vaddr = bitcast i8* %addr to <8 x i64>*
|
|
217 store <8 x i64>%data, <8 x i64>* %vaddr, align 1
|
|
218 ret void
|
|
219 }
|
|
220
|
|
221 define <8 x i64> @test23(i8 * %addr) {
|
120
|
222 ; CHECK-LABEL: test23:
|
|
223 ; CHECK: ## BB#0:
|
|
224 ; CHECK-NEXT: vmovups (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x07]
|
|
225 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
226 %vaddr = bitcast i8* %addr to <8 x i64>*
|
95
|
227 %res = load <8 x i64>, <8 x i64>* %vaddr, align 1
|
77
|
228 ret <8 x i64>%res
|
|
229 }
|
|
230
|
|
231 define void @test24(i8 * %addr, <8 x double> %data) {
|
120
|
232 ; CHECK-LABEL: test24:
|
|
233 ; CHECK: ## BB#0:
|
|
234 ; CHECK-NEXT: vmovaps %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x29,0x07]
|
|
235 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
236 %vaddr = bitcast i8* %addr to <8 x double>*
|
|
237 store <8 x double>%data, <8 x double>* %vaddr, align 64
|
|
238 ret void
|
|
239 }
|
|
240
|
|
241 define <8 x double> @test25(i8 * %addr) {
|
120
|
242 ; CHECK-LABEL: test25:
|
|
243 ; CHECK: ## BB#0:
|
|
244 ; CHECK-NEXT: vmovaps (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]
|
|
245 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
246 %vaddr = bitcast i8* %addr to <8 x double>*
|
95
|
247 %res = load <8 x double>, <8 x double>* %vaddr, align 64
|
77
|
248 ret <8 x double>%res
|
|
249 }
|
|
250
|
|
251 define void @test26(i8 * %addr, <16 x float> %data) {
|
120
|
252 ; CHECK-LABEL: test26:
|
|
253 ; CHECK: ## BB#0:
|
|
254 ; CHECK-NEXT: vmovaps %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x29,0x07]
|
|
255 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
256 %vaddr = bitcast i8* %addr to <16 x float>*
|
|
257 store <16 x float>%data, <16 x float>* %vaddr, align 64
|
|
258 ret void
|
|
259 }
|
|
260
|
|
261 define <16 x float> @test27(i8 * %addr) {
|
120
|
262 ; CHECK-LABEL: test27:
|
|
263 ; CHECK: ## BB#0:
|
|
264 ; CHECK-NEXT: vmovaps (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]
|
|
265 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
266 %vaddr = bitcast i8* %addr to <16 x float>*
|
95
|
267 %res = load <16 x float>, <16 x float>* %vaddr, align 64
|
77
|
268 ret <16 x float>%res
|
|
269 }
|
|
270
|
|
271 define void @test28(i8 * %addr, <8 x double> %data) {
|
120
|
272 ; CHECK-LABEL: test28:
|
|
273 ; CHECK: ## BB#0:
|
|
274 ; CHECK-NEXT: vmovups %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x07]
|
|
275 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
276 %vaddr = bitcast i8* %addr to <8 x double>*
|
|
277 store <8 x double>%data, <8 x double>* %vaddr, align 1
|
|
278 ret void
|
|
279 }
|
|
280
|
|
281 define <8 x double> @test29(i8 * %addr) {
|
120
|
282 ; CHECK-LABEL: test29:
|
|
283 ; CHECK: ## BB#0:
|
|
284 ; CHECK-NEXT: vmovups (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x07]
|
|
285 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
286 %vaddr = bitcast i8* %addr to <8 x double>*
|
95
|
287 %res = load <8 x double>, <8 x double>* %vaddr, align 1
|
77
|
288 ret <8 x double>%res
|
|
289 }
|
|
290
|
|
291 define void @test30(i8 * %addr, <16 x float> %data) {
|
120
|
292 ; CHECK-LABEL: test30:
|
|
293 ; CHECK: ## BB#0:
|
|
294 ; CHECK-NEXT: vmovups %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x07]
|
|
295 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
296 %vaddr = bitcast i8* %addr to <16 x float>*
|
|
297 store <16 x float>%data, <16 x float>* %vaddr, align 1
|
|
298 ret void
|
|
299 }
|
|
300
|
|
301 define <16 x float> @test31(i8 * %addr) {
|
120
|
302 ; CHECK-LABEL: test31:
|
|
303 ; CHECK: ## BB#0:
|
|
304 ; CHECK-NEXT: vmovups (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x07]
|
|
305 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
306 %vaddr = bitcast i8* %addr to <16 x float>*
|
95
|
307 %res = load <16 x float>, <16 x float>* %vaddr, align 1
|
77
|
308 ret <16 x float>%res
|
|
309 }
|
|
310
|
|
311 define <16 x i32> @test32(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
|
120
|
312 ; CHECK-LABEL: test32:
|
|
313 ; CHECK: ## BB#0:
|
121
|
314 ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe9,0xef,0xd2]
|
120
|
315 ; CHECK-NEXT: vpcmpneqd %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf3,0x75,0x48,0x1f,0xca,0x04]
|
121
|
316 ; CHECK-NEXT: vmovdqa32 (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0x6f,0x07]
|
120
|
317 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
318 %mask = icmp ne <16 x i32> %mask1, zeroinitializer
|
|
319 %vaddr = bitcast i8* %addr to <16 x i32>*
|
95
|
320 %r = load <16 x i32>, <16 x i32>* %vaddr, align 64
|
77
|
321 %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old
|
|
322 ret <16 x i32>%res
|
|
323 }
|
|
324
|
|
325 define <16 x i32> @test33(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
|
120
|
326 ; CHECK-LABEL: test33:
|
|
327 ; CHECK: ## BB#0:
|
121
|
328 ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe9,0xef,0xd2]
|
120
|
329 ; CHECK-NEXT: vpcmpneqd %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf3,0x75,0x48,0x1f,0xca,0x04]
|
121
|
330 ; CHECK-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0x7e,0x49,0x6f,0x07]
|
120
|
331 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
332 %mask = icmp ne <16 x i32> %mask1, zeroinitializer
|
|
333 %vaddr = bitcast i8* %addr to <16 x i32>*
|
95
|
334 %r = load <16 x i32>, <16 x i32>* %vaddr, align 1
|
77
|
335 %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old
|
|
336 ret <16 x i32>%res
|
|
337 }
|
|
338
|
|
339 define <16 x i32> @test34(i8 * %addr, <16 x i32> %mask1) {
|
120
|
340 ; CHECK-LABEL: test34:
|
|
341 ; CHECK: ## BB#0:
|
121
|
342 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0xef,0xc9]
|
120
|
343 ; CHECK-NEXT: vpcmpneqd %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf3,0x7d,0x48,0x1f,0xc9,0x04]
|
|
344 ; CHECK-NEXT: vmovdqa32 (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0x6f,0x07]
|
|
345 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
346 %mask = icmp ne <16 x i32> %mask1, zeroinitializer
|
|
347 %vaddr = bitcast i8* %addr to <16 x i32>*
|
95
|
348 %r = load <16 x i32>, <16 x i32>* %vaddr, align 64
|
77
|
349 %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer
|
|
350 ret <16 x i32>%res
|
|
351 }
|
|
352
|
|
353 define <16 x i32> @test35(i8 * %addr, <16 x i32> %mask1) {
|
120
|
354 ; CHECK-LABEL: test35:
|
|
355 ; CHECK: ## BB#0:
|
121
|
356 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0xef,0xc9]
|
120
|
357 ; CHECK-NEXT: vpcmpneqd %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf3,0x7d,0x48,0x1f,0xc9,0x04]
|
|
358 ; CHECK-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0xc9,0x6f,0x07]
|
|
359 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
360 %mask = icmp ne <16 x i32> %mask1, zeroinitializer
|
|
361 %vaddr = bitcast i8* %addr to <16 x i32>*
|
95
|
362 %r = load <16 x i32>, <16 x i32>* %vaddr, align 1
|
77
|
363 %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer
|
|
364 ret <16 x i32>%res
|
|
365 }
|
|
366
|
|
367 define <8 x i64> @test36(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
|
120
|
368 ; CHECK-LABEL: test36:
|
|
369 ; CHECK: ## BB#0:
|
121
|
370 ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe9,0xef,0xd2]
|
120
|
371 ; CHECK-NEXT: vpcmpneqq %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf3,0xf5,0x48,0x1f,0xca,0x04]
|
121
|
372 ; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0x6f,0x07]
|
120
|
373 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
374 %mask = icmp ne <8 x i64> %mask1, zeroinitializer
|
|
375 %vaddr = bitcast i8* %addr to <8 x i64>*
|
95
|
376 %r = load <8 x i64>, <8 x i64>* %vaddr, align 64
|
77
|
377 %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old
|
|
378 ret <8 x i64>%res
|
|
379 }
|
|
380
|
|
381 define <8 x i64> @test37(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
|
120
|
382 ; CHECK-LABEL: test37:
|
|
383 ; CHECK: ## BB#0:
|
121
|
384 ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe9,0xef,0xd2]
|
120
|
385 ; CHECK-NEXT: vpcmpneqq %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf3,0xf5,0x48,0x1f,0xca,0x04]
|
121
|
386 ; CHECK-NEXT: vmovdqu64 (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0xfe,0x49,0x6f,0x07]
|
120
|
387 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
388 %mask = icmp ne <8 x i64> %mask1, zeroinitializer
|
|
389 %vaddr = bitcast i8* %addr to <8 x i64>*
|
95
|
390 %r = load <8 x i64>, <8 x i64>* %vaddr, align 1
|
77
|
391 %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old
|
|
392 ret <8 x i64>%res
|
|
393 }
|
|
394
|
|
395 define <8 x i64> @test38(i8 * %addr, <8 x i64> %mask1) {
|
120
|
396 ; CHECK-LABEL: test38:
|
|
397 ; CHECK: ## BB#0:
|
121
|
398 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0xef,0xc9]
|
120
|
399 ; CHECK-NEXT: vpcmpneqq %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf3,0xfd,0x48,0x1f,0xc9,0x04]
|
|
400 ; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0x6f,0x07]
|
|
401 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
402 %mask = icmp ne <8 x i64> %mask1, zeroinitializer
|
|
403 %vaddr = bitcast i8* %addr to <8 x i64>*
|
95
|
404 %r = load <8 x i64>, <8 x i64>* %vaddr, align 64
|
77
|
405 %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer
|
|
406 ret <8 x i64>%res
|
|
407 }
|
|
408
|
|
409 define <8 x i64> @test39(i8 * %addr, <8 x i64> %mask1) {
|
120
|
410 ; CHECK-LABEL: test39:
|
|
411 ; CHECK: ## BB#0:
|
121
|
412 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0xef,0xc9]
|
120
|
413 ; CHECK-NEXT: vpcmpneqq %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf3,0xfd,0x48,0x1f,0xc9,0x04]
|
|
414 ; CHECK-NEXT: vmovdqu64 (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfe,0xc9,0x6f,0x07]
|
|
415 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
416 %mask = icmp ne <8 x i64> %mask1, zeroinitializer
|
|
417 %vaddr = bitcast i8* %addr to <8 x i64>*
|
95
|
418 %r = load <8 x i64>, <8 x i64>* %vaddr, align 1
|
77
|
419 %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer
|
|
420 ret <8 x i64>%res
|
|
421 }
|
|
422
|
|
423 define <16 x float> @test40(i8 * %addr, <16 x float> %old, <16 x float> %mask1) {
|
120
|
424 ; CHECK-LABEL: test40:
|
|
425 ; CHECK: ## BB#0:
|
121
|
426 ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe8,0x57,0xd2]
|
|
427 ; CHECK-NEXT: vcmpneq_oqps %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf1,0x74,0x48,0xc2,0xca,0x0c]
|
|
428 ; CHECK-NEXT: vmovaps (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x28,0x07]
|
120
|
429 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
430 %mask = fcmp one <16 x float> %mask1, zeroinitializer
|
|
431 %vaddr = bitcast i8* %addr to <16 x float>*
|
95
|
432 %r = load <16 x float>, <16 x float>* %vaddr, align 64
|
77
|
433 %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old
|
|
434 ret <16 x float>%res
|
|
435 }
|
|
436
|
|
437 define <16 x float> @test41(i8 * %addr, <16 x float> %old, <16 x float> %mask1) {
|
120
|
438 ; CHECK-LABEL: test41:
|
|
439 ; CHECK: ## BB#0:
|
121
|
440 ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe8,0x57,0xd2]
|
|
441 ; CHECK-NEXT: vcmpneq_oqps %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf1,0x74,0x48,0xc2,0xca,0x0c]
|
|
442 ; CHECK-NEXT: vmovups (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x10,0x07]
|
120
|
443 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
444 %mask = fcmp one <16 x float> %mask1, zeroinitializer
|
|
445 %vaddr = bitcast i8* %addr to <16 x float>*
|
95
|
446 %r = load <16 x float>, <16 x float>* %vaddr, align 1
|
77
|
447 %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old
|
|
448 ret <16 x float>%res
|
|
449 }
|
|
450
|
|
451 define <16 x float> @test42(i8 * %addr, <16 x float> %mask1) {
|
120
|
452 ; CHECK-LABEL: test42:
|
|
453 ; CHECK: ## BB#0:
|
121
|
454 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf0,0x57,0xc9]
|
|
455 ; CHECK-NEXT: vcmpneq_oqps %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf1,0x7c,0x48,0xc2,0xc9,0x0c]
|
120
|
456 ; CHECK-NEXT: vmovaps (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x28,0x07]
|
|
457 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
458 %mask = fcmp one <16 x float> %mask1, zeroinitializer
|
|
459 %vaddr = bitcast i8* %addr to <16 x float>*
|
95
|
460 %r = load <16 x float>, <16 x float>* %vaddr, align 64
|
77
|
461 %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer
|
|
462 ret <16 x float>%res
|
|
463 }
|
|
464
|
|
465 define <16 x float> @test43(i8 * %addr, <16 x float> %mask1) {
|
120
|
466 ; CHECK-LABEL: test43:
|
|
467 ; CHECK: ## BB#0:
|
121
|
468 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf0,0x57,0xc9]
|
|
469 ; CHECK-NEXT: vcmpneq_oqps %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf1,0x7c,0x48,0xc2,0xc9,0x0c]
|
120
|
470 ; CHECK-NEXT: vmovups (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x10,0x07]
|
|
471 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
472 %mask = fcmp one <16 x float> %mask1, zeroinitializer
|
|
473 %vaddr = bitcast i8* %addr to <16 x float>*
|
95
|
474 %r = load <16 x float>, <16 x float>* %vaddr, align 1
|
77
|
475 %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer
|
|
476 ret <16 x float>%res
|
|
477 }
|
|
478
|
|
479 define <8 x double> @test44(i8 * %addr, <8 x double> %old, <8 x double> %mask1) {
|
120
|
480 ; CHECK-LABEL: test44:
|
|
481 ; CHECK: ## BB#0:
|
121
|
482 ; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe9,0x57,0xd2]
|
|
483 ; CHECK-NEXT: vcmpneq_oqpd %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf1,0xf5,0x48,0xc2,0xca,0x0c]
|
|
484 ; CHECK-NEXT: vmovapd (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0x28,0x07]
|
120
|
485 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
486 %mask = fcmp one <8 x double> %mask1, zeroinitializer
|
|
487 %vaddr = bitcast i8* %addr to <8 x double>*
|
95
|
488 %r = load <8 x double>, <8 x double>* %vaddr, align 64
|
77
|
489 %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old
|
|
490 ret <8 x double>%res
|
|
491 }
|
|
492
|
|
493 define <8 x double> @test45(i8 * %addr, <8 x double> %old, <8 x double> %mask1) {
|
120
|
494 ; CHECK-LABEL: test45:
|
|
495 ; CHECK: ## BB#0:
|
121
|
496 ; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe9,0x57,0xd2]
|
|
497 ; CHECK-NEXT: vcmpneq_oqpd %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf1,0xf5,0x48,0xc2,0xca,0x0c]
|
|
498 ; CHECK-NEXT: vmovupd (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0x10,0x07]
|
120
|
499 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
500 %mask = fcmp one <8 x double> %mask1, zeroinitializer
|
|
501 %vaddr = bitcast i8* %addr to <8 x double>*
|
95
|
502 %r = load <8 x double>, <8 x double>* %vaddr, align 1
|
77
|
503 %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old
|
|
504 ret <8 x double>%res
|
|
505 }
|
|
506
|
|
507 define <8 x double> @test46(i8 * %addr, <8 x double> %mask1) {
|
120
|
508 ; CHECK-LABEL: test46:
|
|
509 ; CHECK: ## BB#0:
|
121
|
510 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x57,0xc9]
|
|
511 ; CHECK-NEXT: vcmpneq_oqpd %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf1,0xfd,0x48,0xc2,0xc9,0x0c]
|
120
|
512 ; CHECK-NEXT: vmovapd (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0x28,0x07]
|
|
513 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
514 %mask = fcmp one <8 x double> %mask1, zeroinitializer
|
|
515 %vaddr = bitcast i8* %addr to <8 x double>*
|
95
|
516 %r = load <8 x double>, <8 x double>* %vaddr, align 64
|
77
|
517 %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer
|
|
518 ret <8 x double>%res
|
|
519 }
|
|
520
|
|
521 define <8 x double> @test47(i8 * %addr, <8 x double> %mask1) {
|
120
|
522 ; CHECK-LABEL: test47:
|
|
523 ; CHECK: ## BB#0:
|
121
|
524 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x57,0xc9]
|
|
525 ; CHECK-NEXT: vcmpneq_oqpd %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf1,0xfd,0x48,0xc2,0xc9,0x0c]
|
120
|
526 ; CHECK-NEXT: vmovupd (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0x10,0x07]
|
|
527 ; CHECK-NEXT: retq ## encoding: [0xc3]
|
77
|
528 %mask = fcmp one <8 x double> %mask1, zeroinitializer
|
|
529 %vaddr = bitcast i8* %addr to <8 x double>*
|
95
|
530 %r = load <8 x double>, <8 x double>* %vaddr, align 1
|
77
|
531 %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer
|
|
532 ret <8 x double>%res
|
|
533 }
|