comparison lib/Target/PowerPC/PPCInstrQPX.td @ 120:1172e4bd9c6f

update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
86 (pre_truncst node:$val, 86 (pre_truncst node:$val,
87 node:$base, node:$offset), [{ 87 node:$base, node:$offset), [{
88 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4f32; 88 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4f32;
89 }]>; 89 }]>;
90 90
91 def fround_inexact : PatFrag<(ops node:$val), (fround node:$val), [{ 91 def fround_inexact : PatFrag<(ops node:$val), (fpround node:$val), [{
92 return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() == 0; 92 return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() == 0;
93 }]>; 93 }]>;
94 94
95 def fround_exact : PatFrag<(ops node:$val), (fround node:$val), [{ 95 def fround_exact : PatFrag<(ops node:$val), (fpround node:$val), [{
96 return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() == 1; 96 return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() == 1;
97 }]>; 97 }]>;
98 98
99 let FastIselShouldIgnore = 1 in // FastIsel should ignore all u12 instrs. 99 let FastIselShouldIgnore = 1 in // FastIsel should ignore all u12 instrs.
100 def u12 : ImmLeaf<i32, [{ return (Imm & 0xFFF) == Imm; }]>; 100 def u12 : ImmLeaf<i32, [{ return (Imm & 0xFFF) == Imm; }]>;
309 "qvfriz $FRT, $FRB", IIC_FPGeneral, 309 "qvfriz $FRT, $FRB", IIC_FPGeneral,
310 [(set v4f32:$FRT, (ftrunc v4f32:$FRB))]>; 310 [(set v4f32:$FRT, (ftrunc v4f32:$FRB))]>;
311 311
312 def QVFRIN : XForm_19<4, 392, (outs qfrc:$FRT), (ins qfrc:$FRB), 312 def QVFRIN : XForm_19<4, 392, (outs qfrc:$FRT), (ins qfrc:$FRB),
313 "qvfrin $FRT, $FRB", IIC_FPGeneral, 313 "qvfrin $FRT, $FRB", IIC_FPGeneral,
314 [(set v4f64:$FRT, (frnd v4f64:$FRB))]>; 314 [(set v4f64:$FRT, (fround v4f64:$FRB))]>;
315 let isCodeGenOnly = 1 in 315 let isCodeGenOnly = 1 in
316 def QVFRINs : XForm_19<4, 392, (outs qsrc:$FRT), (ins qsrc:$FRB), 316 def QVFRINs : XForm_19<4, 392, (outs qsrc:$FRT), (ins qsrc:$FRB),
317 "qvfrin $FRT, $FRB", IIC_FPGeneral, 317 "qvfrin $FRT, $FRB", IIC_FPGeneral,
318 [(set v4f32:$FRT, (frnd v4f32:$FRB))]>; 318 [(set v4f32:$FRT, (fround v4f32:$FRB))]>;
319 319
320 def QVFRIP : XForm_19<4, 456, (outs qfrc:$FRT), (ins qfrc:$FRB), 320 def QVFRIP : XForm_19<4, 456, (outs qfrc:$FRT), (ins qfrc:$FRB),
321 "qvfrip $FRT, $FRB", IIC_FPGeneral, 321 "qvfrip $FRT, $FRB", IIC_FPGeneral,
322 [(set v4f64:$FRT, (fceil v4f64:$FRB))]>; 322 [(set v4f64:$FRT, (fceil v4f64:$FRB))]>;
323 let isCodeGenOnly = 1 in 323 let isCodeGenOnly = 1 in
1101 def : Pat<(xor v4i1:$FRA, v4i1:$FRB), 1101 def : Pat<(xor v4i1:$FRA, v4i1:$FRB),
1102 (QVFLOGICALb $FRA, $FRB, (i32 6))>; 1102 (QVFLOGICALb $FRA, $FRB, (i32 6))>;
1103 def : Pat<(not v4i1:$FRA), 1103 def : Pat<(not v4i1:$FRA),
1104 (QVFLOGICALb $FRA, $FRA, (i32 10))>; 1104 (QVFLOGICALb $FRA, $FRA, (i32 10))>;
1105 1105
1106 def : Pat<(v4f64 (fextend v4f32:$src)), 1106 def : Pat<(v4f64 (fpextend v4f32:$src)),
1107 (COPY_TO_REGCLASS $src, QFRC)>; 1107 (COPY_TO_REGCLASS $src, QFRC)>;
1108 1108
1109 def : Pat<(v4f32 (fround_exact v4f64:$src)), 1109 def : Pat<(v4f32 (fround_exact v4f64:$src)),
1110 (COPY_TO_REGCLASS $src, QSRC)>; 1110 (COPY_TO_REGCLASS $src, QSRC)>;
1111 1111