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comparison test/CodeGen/AArch64/cond-sel.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 54457678186b
children
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s --check-prefix=CHECK 1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s 2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
3 3
4 @var32 = global i32 0 4 @var32 = global i32 0
5 @var64 = global i64 0 5 @var64 = global i64 0
6 6
8 ; CHECK-LABEL: test_csel: 8 ; CHECK-LABEL: test_csel:
9 9
10 %tst1 = icmp ugt i32 %lhs32, %rhs32 10 %tst1 = icmp ugt i32 %lhs32, %rhs32
11 %val1 = select i1 %tst1, i32 42, i32 52 11 %val1 = select i1 %tst1, i32 42, i32 52
12 store i32 %val1, i32* @var32 12 store i32 %val1, i32* @var32
13 ; CHECK-DAG: movz [[W52:w[0-9]+]], #{{52|0x34}} 13 ; CHECK-DAG: mov [[W52:w[0-9]+]], #{{52|0x34}}
14 ; CHECK-DAG: movz [[W42:w[0-9]+]], #{{42|0x2a}} 14 ; CHECK-DAG: mov [[W42:w[0-9]+]], #{{42|0x2a}}
15 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi 15 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi
16 16
17 %rhs64 = sext i32 %rhs32 to i64 17 %rhs64 = sext i32 %rhs32 to i64
18 %tst2 = icmp sle i64 %lhs64, %rhs64 18 %tst2 = icmp sle i64 %lhs64, %rhs64
19 %val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64 19 %val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64
32 %tst1 = fcmp one float %lhs32, %rhs32 32 %tst1 = fcmp one float %lhs32, %rhs32
33 ; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}} 33 ; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
34 ; CHECK-NOFP-NOT: fcmp 34 ; CHECK-NOFP-NOT: fcmp
35 %val1 = select i1 %tst1, i32 42, i32 52 35 %val1 = select i1 %tst1, i32 42, i32 52
36 store i32 %val1, i32* @var32 36 store i32 %val1, i32* @var32
37 ; CHECK: movz [[W52:w[0-9]+]], #{{52|0x34}} 37 ; CHECK: mov [[W52:w[0-9]+]], #{{52|0x34}}
38 ; CHECK: movz [[W42:w[0-9]+]], #{{42|0x2a}} 38 ; CHECK: mov [[W42:w[0-9]+]], #{{42|0x2a}}
39 ; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi 39 ; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi
40 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt 40 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt
41 41
42 42
43 %tst2 = fcmp ueq double %lhs64, %rhs64 43 %tst2 = fcmp ueq double %lhs64, %rhs64
44 ; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}} 44 ; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
45 ; CHECK-NOFP-NOT: fcmp 45 ; CHECK-NOFP-NOT: fcmp
46 %val2 = select i1 %tst2, i64 9, i64 15 46 %val2 = select i1 %tst2, i64 9, i64 15
47 store i64 %val2, i64* @var64 47 store i64 %val2, i64* @var64
48 ; CHECK: orr w[[CONST15:[0-9]+]], wzr, #0xf 48 ; CHECK: orr w[[CONST15:[0-9]+]], wzr, #0xf
49 ; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}} 49 ; CHECK: mov {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}}
50 ; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq 50 ; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq
51 ; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs 51 ; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs
52 52
53 ret void 53 ret void
54 ; CHECK: ret 54 ; CHECK: ret
133 133
134 ret void 134 ret void
135 ; CHECK: ret 135 ; CHECK: ret
136 } 136 }
137 137
138 define void @test_csinv0(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) minsize {
139 ; CHECK-LABEL: test_csinv0:
140
141 %tst1 = icmp ugt i32 %lhs32, %rhs32
142 %val1 = select i1 %tst1, i32 0, i32 -1
143 store volatile i32 %val1, i32* @var32
144 ; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
145 ; CHECK: csetm {{w[0-9]+}}, ls
146
147 %rhs2 = add i32 %rhs32, 42
148 %tst2 = icmp sle i32 %lhs32, %rhs2
149 %val2 = select i1 %tst2, i32 -1, i32 %rhs2
150 store volatile i32 %val2, i32* @var32
151 ; CHECK: cmp [[LHS2:w[0-9]+]], [[RHS2:w[0-9]+]]
152 ; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt
153
154 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
155 %rhs3 = mul i64 %rhs64, 19
156 %tst3 = icmp ugt i64 %lhs64, %rhs3
157 %val3 = select i1 %tst3, i64 %rhs3, i64 -1
158 store volatile i64 %val3, i64* @var64
159 ; CHECK: cmp [[LHS3:x[0-9]+]], [[RHS3:x[0-9]+]]
160 ; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi
161
162 ret void
163 ; CHECK: ret
164 }
165
138 define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize { 166 define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
139 ; CHECK-LABEL: test_csneg: 167 ; CHECK-LABEL: test_csneg:
140 168
141 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). 169 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
142 %tst1 = icmp ugt i32 %lhs32, %rhs32 170 %tst1 = icmp ugt i32 %lhs32, %rhs32