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comparison test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
2 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
3
4 ; and can be eliminated
5 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range:
6 ; CHECK-NOT: v0
7 ; CHECK: {{flat|buffer}}_store_dword {{.*}}v0
8 define void @test_workitem_id_x_known_max_range(i32 addrspace(1)* nocapture %out) #0 {
9 entry:
10 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
11 %and = and i32 %id, 1023
12 store i32 %and, i32 addrspace(1)* %out, align 4
13 ret void
14 }
15
16 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_trunc_1_bit_range:
17 ; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x1ff, v0
18 ; CHECK: {{flat|buffer}}_store_dword {{.*}}[[MASKED]]
19 define void @test_workitem_id_x_known_trunc_1_bit_range(i32 addrspace(1)* nocapture %out) #0 {
20 entry:
21 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
22 %and = and i32 %id, 511
23 store i32 %and, i32 addrspace(1)* %out, align 4
24 ret void
25 }
26
27 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range_m1:
28 ; CHECK-NOT: v0
29 ; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xff, v0
30 ; CHECK: {{flat|buffer}}_store_dword {{.*}}[[MASKED]]
31 define void @test_workitem_id_x_known_max_range_m1(i32 addrspace(1)* nocapture %out) #0 {
32 entry:
33 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !1
34 %and = and i32 %id, 255
35 store i32 %and, i32 addrspace(1)* %out, align 4
36 ret void
37 }
38
39
40 declare i32 @llvm.amdgcn.workitem.id.x() #1
41
42 attributes #0 = { norecurse nounwind }
43 attributes #1 = { nounwind readnone }
44
45 !0 = !{i32 0, i32 1024}
46 !1 = !{i32 0, i32 1023}