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comparison test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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children 803732b1fca8
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101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
3
4 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
5 declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
6
7 ; FUNC-LABEL: {{^}}test_umul24_i32:
8 ; GCN: v_mul_u32_u24
9 define void @test_umul24_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
10 entry:
11 %0 = shl i32 %a, 8
12 %a_24 = lshr i32 %0, 8
13 %1 = shl i32 %b, 8
14 %b_24 = lshr i32 %1, 8
15 %2 = mul i32 %a_24, %b_24
16 store i32 %2, i32 addrspace(1)* %out
17 ret void
18 }
19
20 ; FUNC-LABEL: {{^}}test_umul24_i16_sext:
21 ; SI: v_mul_u32_u24_e{{(32|64)}} [[VI_MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
22 ; SI: v_bfe_i32 v{{[0-9]}}, [[VI_MUL]], 0, 16
23 ; VI: s_mul_i32 [[SI_MUL:s[0-9]]], s{{[0-9]}}, s{{[0-9]}}
24 ; VI: s_sext_i32_i16 s{{[0-9]}}, [[SI_MUL]]
25 define void @test_umul24_i16_sext(i32 addrspace(1)* %out, i16 %a, i16 %b) {
26 entry:
27 %mul = mul i16 %a, %b
28 %ext = sext i16 %mul to i32
29 store i32 %ext, i32 addrspace(1)* %out
30 ret void
31 }
32
33 ; FUNC-LABEL: {{^}}test_umul24_i16_vgpr_sext:
34 ; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
35 ; VI: v_mul_lo_u16_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
36 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 16
37 define void @test_umul24_i16_vgpr_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
38 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
39 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()
40 %ptr_a = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.x
41 %ptr_b = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.y
42 %a = load i16, i16 addrspace(1)* %ptr_a
43 %b = load i16, i16 addrspace(1)* %ptr_b
44 %mul = mul i16 %a, %b
45 %val = sext i16 %mul to i32
46 store i32 %val, i32 addrspace(1)* %out
47 ret void
48 }
49
50 ; FUNC-LABEL: {{^}}test_umul24_i16:
51 ; SI: s_and_b32
52 ; SI: v_mul_u32_u24_e32
53 ; SI: v_and_b32_e32
54 ; VI: s_mul_i32
55 ; VI: s_and_b32
56 ; VI: v_mov_b32_e32
57 define void @test_umul24_i16(i32 addrspace(1)* %out, i16 %a, i16 %b) {
58 entry:
59 %mul = mul i16 %a, %b
60 %ext = zext i16 %mul to i32
61 store i32 %ext, i32 addrspace(1)* %out
62 ret void
63 }
64
65 ; FUNC-LABEL: {{^}}test_umul24_i16_vgpr:
66 ; SI: v_mul_u32_u24_e32
67 ; SI: v_and_b32_e32
68 ; VI: v_mul_lo_u16
69 define void @test_umul24_i16_vgpr(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
70 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
71 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()
72 %ptr_a = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.x
73 %ptr_b = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.y
74 %a = load i16, i16 addrspace(1)* %ptr_a
75 %b = load i16, i16 addrspace(1)* %ptr_b
76 %mul = mul i16 %a, %b
77 %val = zext i16 %mul to i32
78 store i32 %val, i32 addrspace(1)* %out
79 ret void
80 }
81
82 ; FUNC-LABEL: {{^}}test_umul24_i8_vgpr:
83 ; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
84 ; VI: v_mul_lo_u16_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
85 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
86 define void @test_umul24_i8_vgpr(i32 addrspace(1)* %out, i8 addrspace(1)* %a, i8 addrspace(1)* %b) {
87 entry:
88 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
89 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()
90 %a.ptr = getelementptr i8, i8 addrspace(1)* %a, i32 %tid.x
91 %b.ptr = getelementptr i8, i8 addrspace(1)* %b, i32 %tid.y
92 %a.l = load i8, i8 addrspace(1)* %a.ptr
93 %b.l = load i8, i8 addrspace(1)* %b.ptr
94 %mul = mul i8 %a.l, %b.l
95 %ext = sext i8 %mul to i32
96 store i32 %ext, i32 addrspace(1)* %out
97 ret void
98 }
99
100 ; FUNC-LABEL: {{^}}test_umulhi24_i32_i64:
101 ; GCN-NOT: and
102 ; GCN: v_mul_hi_u32_u24_e32 [[RESULT:v[0-9]+]],
103 ; GCN-NEXT: buffer_store_dword [[RESULT]]
104 define void @test_umulhi24_i32_i64(i32 addrspace(1)* %out, i32 %a, i32 %b) {
105 entry:
106 %a.24 = and i32 %a, 16777215
107 %b.24 = and i32 %b, 16777215
108 %a.24.i64 = zext i32 %a.24 to i64
109 %b.24.i64 = zext i32 %b.24 to i64
110 %mul48 = mul i64 %a.24.i64, %b.24.i64
111 %mul48.hi = lshr i64 %mul48, 32
112 %mul24hi = trunc i64 %mul48.hi to i32
113 store i32 %mul24hi, i32 addrspace(1)* %out
114 ret void
115 }
116
117 ; FUNC-LABEL: {{^}}test_umulhi24:
118 ; GCN-NOT: and
119 ; GCN: v_mul_hi_u32_u24_e32 [[RESULT:v[0-9]+]],
120 ; GCN-NEXT: buffer_store_dword [[RESULT]]
121 define void @test_umulhi24(i32 addrspace(1)* %out, i64 %a, i64 %b) {
122 entry:
123 %a.24 = and i64 %a, 16777215
124 %b.24 = and i64 %b, 16777215
125 %mul48 = mul i64 %a.24, %b.24
126 %mul48.hi = lshr i64 %mul48, 32
127 %mul24.hi = trunc i64 %mul48.hi to i32
128 store i32 %mul24.hi, i32 addrspace(1)* %out
129 ret void
130 }
131
132 ; Multiply with 24-bit inputs and 64-bit output.
133 ; FUNC-LABEL: {{^}}test_umul24_i64:
134 ; GCN-NOT: and
135 ; GCN-NOT: lshr
136 ; GCN-DAG: v_mul_u32_u24_e32
137 ; GCN-DAG: v_mul_hi_u32_u24_e32
138 ; GCN: buffer_store_dwordx2
139 define void @test_umul24_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
140 entry:
141 %tmp0 = shl i64 %a, 40
142 %a_24 = lshr i64 %tmp0, 40
143 %tmp1 = shl i64 %b, 40
144 %b_24 = lshr i64 %tmp1, 40
145 %tmp2 = mul i64 %a_24, %b_24
146 store i64 %tmp2, i64 addrspace(1)* %out
147 ret void
148 }
149
150 ; FUNC-LABEL: {{^}}test_umul24_i64_square:
151 ; GCN: s_load_dword [[A:s[0-9]+]]
152 ; GCN-NOT: s_and_b32
153 ; GCN-DAG: v_mul_hi_u32_u24_e64 v{{[0-9]+}}, [[A]], [[A]]
154 ; GCN-DAG: v_mul_u32_u24_e64 v{{[0-9]+}}, [[A]], [[A]]
155 define void @test_umul24_i64_square(i64 addrspace(1)* %out, i64 %a) {
156 entry:
157 %tmp0 = shl i64 %a, 40
158 %a.24 = lshr i64 %tmp0, 40
159 %tmp2 = mul i64 %a.24, %a.24
160 store i64 %tmp2, i64 addrspace(1)* %out
161 ret void
162 }
163
164 ; FUNC-LABEL: {{^}}test_umulhi16_i32:
165 ; GCN: s_and_b32
166 ; GCN: s_and_b32
167 ; GCN: v_mul_u32_u24_e32 [[MUL24:v[0-9]+]]
168 ; GCN: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[MUL24]]
169 define void @test_umulhi16_i32(i16 addrspace(1)* %out, i32 %a, i32 %b) {
170 entry:
171 %a.16 = and i32 %a, 65535
172 %b.16 = and i32 %b, 65535
173 %mul = mul i32 %a.16, %b.16
174 %hi = lshr i32 %mul, 16
175 %mulhi = trunc i32 %hi to i16
176 store i16 %mulhi, i16 addrspace(1)* %out
177 ret void
178 }
179
180 ; FUNC-LABEL: {{^}}test_umul24_i33:
181 ; GCN: s_load_dword s
182 ; GCN: s_load_dword s
183 ; GCN-NOT: and
184 ; GCN-NOT: lshr
185 ; GCN-DAG: v_mul_u32_u24_e32 v[[MUL_LO:[0-9]+]],
186 ; GCN-DAG: v_mul_hi_u32_u24_e32 v[[MUL_HI:[0-9]+]],
187 ; GCN-DAG: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
188 ; GCN: buffer_store_dwordx2 v{{\[}}[[MUL_LO]]:[[HI]]{{\]}}
189 define void @test_umul24_i33(i64 addrspace(1)* %out, i33 %a, i33 %b) {
190 entry:
191 %tmp0 = shl i33 %a, 9
192 %a_24 = lshr i33 %tmp0, 9
193 %tmp1 = shl i33 %b, 9
194 %b_24 = lshr i33 %tmp1, 9
195 %tmp2 = mul i33 %a_24, %b_24
196 %ext = zext i33 %tmp2 to i64
197 store i64 %ext, i64 addrspace(1)* %out
198 ret void
199 }
200
201 ; FUNC-LABEL: {{^}}test_umulhi24_i33:
202 ; GCN: s_load_dword s
203 ; GCN: s_load_dword s
204 ; GCN-NOT: and
205 ; GCN-NOT: lshr
206 ; GCN: v_mul_hi_u32_u24_e32 v[[MUL_HI:[0-9]+]],
207 ; GCN-NEXT: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
208 ; GCN-NEXT: buffer_store_dword v[[HI]]
209 define void @test_umulhi24_i33(i32 addrspace(1)* %out, i33 %a, i33 %b) {
210 entry:
211 %tmp0 = shl i33 %a, 9
212 %a_24 = lshr i33 %tmp0, 9
213 %tmp1 = shl i33 %b, 9
214 %b_24 = lshr i33 %tmp1, 9
215 %tmp2 = mul i33 %a_24, %b_24
216 %hi = lshr i33 %tmp2, 32
217 %trunc = trunc i33 %hi to i32
218 store i32 %trunc, i32 addrspace(1)* %out
219 ret void
220 }