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comparison test/CodeGen/ARM/cmpxchg-weak.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
4 ; CHECK-LABEL: test_cmpxchg_weak: 4 ; CHECK-LABEL: test_cmpxchg_weak:
5 5
6 %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic 6 %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
7 %oldval = extractvalue { i32, i1 } %pair, 0 7 %oldval = extractvalue { i32, i1 } %pair, 0
8 ; CHECK-NEXT: BB#0: 8 ; CHECK-NEXT: BB#0:
9 ; CHECK-NEXT: dmb ish
10 ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0] 9 ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0]
11 ; CHECK-NEXT: cmp [[LOADED]], r1 10 ; CHECK-NEXT: cmp [[LOADED]], r1
12 ; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]] 11 ; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
13 ; CHECK-NEXT: BB#1: 12 ; CHECK-NEXT: BB#1:
13 ; CHECK-NEXT: dmb ish
14 ; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0] 14 ; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0]
15 ; CHECK-NEXT: cmp [[SUCCESS]], #0 15 ; CHECK-NEXT: cmp [[SUCCESS]], #0
16 ; CHECK-NEXT: bne [[FAILBB:LBB[0-9]+_[0-9]+]] 16 ; CHECK-NEXT: bne [[FAILBB:LBB[0-9]+_[0-9]+]]
17 ; CHECK-NEXT: BB#2: 17 ; CHECK-NEXT: BB#2:
18 ; CHECK-NEXT: dmb ish 18 ; CHECK-NEXT: dmb ish
34 34
35 %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic 35 %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
36 %success = extractvalue { i32, i1 } %pair, 1 36 %success = extractvalue { i32, i1 } %pair, 1
37 37
38 ; CHECK-NEXT: BB#0: 38 ; CHECK-NEXT: BB#0:
39 ; CHECK-NEXT: dmb ish
40 ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1] 39 ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1]
41 ; CHECK-NEXT: cmp [[LOADED]], r2 40 ; CHECK-NEXT: cmp [[LOADED]], r2
42 ; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]] 41 ; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
43 ; CHECK-NEXT: BB#1: 42 ; CHECK-NEXT: BB#1:
43 ; CHECK-NEXT: dmb ish
44 ; CHECK-NEXT: mov r0, #0
44 ; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1] 45 ; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1]
45 ; CHECK-NEXT: mov r0, #0
46 ; CHECK-NEXT: cmp [[SUCCESS]], #0 46 ; CHECK-NEXT: cmp [[SUCCESS]], #0
47 ; CHECK-NEXT: bxne lr 47 ; CHECK-NEXT: bxne lr
48 ; CHECK-NEXT: dmb ish 48 ; CHECK-NEXT: dmb ish
49 ; CHECK-NEXT: mov r0, #1 49 ; CHECK-NEXT: mov r0, #1
50 ; CHECK-NEXT: bx lr 50 ; CHECK-NEXT: bx lr