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comparison test/CodeGen/Mips/fpbr.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
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101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC 1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC
2 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC 2 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC
3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR 3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
4 ; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC 4 ; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC
5 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC 5 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR 6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
7 7
8 define void @func0(float %f2, float %f3) nounwind { 8 define void @func0(float %f2, float %f3) nounwind {
9 entry: 9 entry:
10 ; ALL-LABEL: func0: 10 ; ALL-LABEL: func0:
11 11
12 ; 32-FCC: c.eq.s $f12, $f14 12 ; 32-FCC: c.eq.s $f12, $f14
13 ; 32-FCC: bc1f $BB0_2
13 ; 64-FCC: c.eq.s $f12, $f13 14 ; 64-FCC: c.eq.s $f12, $f13
14 ; FCC: bc1f $BB0_2 15 ; 64-FCC: bc1f .LBB0_2
15 16
16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14 17 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13 18 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
18 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] 19 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
19 ; FIXME: We ought to be able to transform not+bnez -> beqz 20 ; FIXME: We ought to be able to transform not+bnez -> beqz
20 ; GPR: not $[[GPRCC]], $[[GPRCC]] 21 ; GPR: not $[[GPRCC]], $[[GPRCC]]
21 ; GPR: bnez $[[GPRCC]], $BB0_2 22 ; 32-GPR: bnez $[[GPRCC]], $BB0_2
23 ; 64-GPR: bnezc $[[GPRCC]], .LBB0_2
22 24
23 %cmp = fcmp oeq float %f2, %f3 25 %cmp = fcmp oeq float %f2, %f3
24 br i1 %cmp, label %if.then, label %if.else 26 br i1 %cmp, label %if.then, label %if.else
25 27
26 if.then: ; preds = %entry 28 if.then: ; preds = %entry
42 define void @func1(float %f2, float %f3) nounwind { 44 define void @func1(float %f2, float %f3) nounwind {
43 entry: 45 entry:
44 ; ALL-LABEL: func1: 46 ; ALL-LABEL: func1:
45 47
46 ; 32-FCC: c.olt.s $f12, $f14 48 ; 32-FCC: c.olt.s $f12, $f14
49 ; 32-FCC: bc1f $BB1_2
47 ; 64-FCC: c.olt.s $f12, $f13 50 ; 64-FCC: c.olt.s $f12, $f13
48 ; FCC: bc1f $BB1_2 51 ; 64-FCC: bc1f .LBB1_2
49 52
50 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12 53 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
51 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12 54 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
52 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] 55 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
53 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] 56 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
54 ; GPR: bnez $[[GPRCC]], $BB1_2 57 ; 32-GPR: bnez $[[GPRCC]], $BB1_2
58 ; 64-GPR: bnezc $[[GPRCC]], .LBB1_2
55 59
56 %cmp = fcmp olt float %f2, %f3 60 %cmp = fcmp olt float %f2, %f3
57 br i1 %cmp, label %if.then, label %if.else 61 br i1 %cmp, label %if.then, label %if.else
58 62
59 if.then: ; preds = %entry 63 if.then: ; preds = %entry
71 define void @func2(float %f2, float %f3) nounwind { 75 define void @func2(float %f2, float %f3) nounwind {
72 entry: 76 entry:
73 ; ALL-LABEL: func2: 77 ; ALL-LABEL: func2:
74 78
75 ; 32-FCC: c.ole.s $f12, $f14 79 ; 32-FCC: c.ole.s $f12, $f14
80 ; 32-FCC: bc1t $BB2_2
76 ; 64-FCC: c.ole.s $f12, $f13 81 ; 64-FCC: c.ole.s $f12, $f13
77 ; FCC: bc1t $BB2_2 82 ; 64-FCC: bc1t .LBB2_2
78 83
79 ; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12 84 ; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12
80 ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12 85 ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
81 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] 86 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
82 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] 87 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
83 ; GPR: beqz $[[GPRCC]], $BB2_2 88 ; 32-GPR: beqz $[[GPRCC]], $BB2_2
89 ; 64-GPR: beqzc $[[GPRCC]], .LBB2_2
84 90
85 %cmp = fcmp ugt float %f2, %f3 91 %cmp = fcmp ugt float %f2, %f3
86 br i1 %cmp, label %if.else, label %if.then 92 br i1 %cmp, label %if.else, label %if.then
87 93
88 if.then: ; preds = %entry 94 if.then: ; preds = %entry
100 define void @func3(double %f2, double %f3) nounwind { 106 define void @func3(double %f2, double %f3) nounwind {
101 entry: 107 entry:
102 ; ALL-LABEL: func3: 108 ; ALL-LABEL: func3:
103 109
104 ; 32-FCC: c.eq.d $f12, $f14 110 ; 32-FCC: c.eq.d $f12, $f14
111 ; 32-FCC: bc1f $BB3_2
105 ; 64-FCC: c.eq.d $f12, $f13 112 ; 64-FCC: c.eq.d $f12, $f13
106 ; FCC: bc1f $BB3_2 113 ; 64-FCC: bc1f .LBB3_2
107 114
108 ; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14 115 ; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14
109 ; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13 116 ; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
110 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] 117 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
111 ; FIXME: We ought to be able to transform not+bnez -> beqz 118 ; FIXME: We ought to be able to transform not+bnez -> beqz
112 ; GPR: not $[[GPRCC]], $[[GPRCC]] 119 ; GPR: not $[[GPRCC]], $[[GPRCC]]
113 ; GPR: bnez $[[GPRCC]], $BB3_2 120 ; 32-GPR: bnez $[[GPRCC]], $BB3_2
121 ; 64-GPR: bnezc $[[GPRCC]], .LBB3_2
114 122
115 %cmp = fcmp oeq double %f2, %f3 123 %cmp = fcmp oeq double %f2, %f3
116 br i1 %cmp, label %if.then, label %if.else 124 br i1 %cmp, label %if.then, label %if.else
117 125
118 if.then: ; preds = %entry 126 if.then: ; preds = %entry
130 define void @func4(double %f2, double %f3) nounwind { 138 define void @func4(double %f2, double %f3) nounwind {
131 entry: 139 entry:
132 ; ALL-LABEL: func4: 140 ; ALL-LABEL: func4:
133 141
134 ; 32-FCC: c.olt.d $f12, $f14 142 ; 32-FCC: c.olt.d $f12, $f14
143 ; 32-FCC: bc1f $BB4_2
135 ; 64-FCC: c.olt.d $f12, $f13 144 ; 64-FCC: c.olt.d $f12, $f13
136 ; FCC: bc1f $BB4_2 145 ; 64-FCC: bc1f .LBB4_2
137 146
138 ; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12 147 ; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12
139 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12 148 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
140 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] 149 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
141 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] 150 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
142 ; GPR: bnez $[[GPRCC]], $BB4_2 151 ; 32-GPR: bnez $[[GPRCC]], $BB4_2
152 ; 64-GPR: bnezc $[[GPRCC]], .LBB4_2
143 153
144 %cmp = fcmp olt double %f2, %f3 154 %cmp = fcmp olt double %f2, %f3
145 br i1 %cmp, label %if.then, label %if.else 155 br i1 %cmp, label %if.then, label %if.else
146 156
147 if.then: ; preds = %entry 157 if.then: ; preds = %entry
159 define void @func5(double %f2, double %f3) nounwind { 169 define void @func5(double %f2, double %f3) nounwind {
160 entry: 170 entry:
161 ; ALL-LABEL: func5: 171 ; ALL-LABEL: func5:
162 172
163 ; 32-FCC: c.ole.d $f12, $f14 173 ; 32-FCC: c.ole.d $f12, $f14
174 ; 32-FCC: bc1t $BB5_2
164 ; 64-FCC: c.ole.d $f12, $f13 175 ; 64-FCC: c.ole.d $f12, $f13
165 ; FCC: bc1t $BB5_2 176 ; 64-FCC: bc1t .LBB5_2
166 177
167 ; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12 178 ; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12
168 ; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12 179 ; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12
169 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] 180 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
170 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] 181 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
171 ; GPR: beqz $[[GPRCC]], $BB5_2 182 ; 32-GPR: beqz $[[GPRCC]], $BB5_2
183 ; 64-GPR: beqzc $[[GPRCC]], .LBB5_2
172 184
173 %cmp = fcmp ugt double %f2, %f3 185 %cmp = fcmp ugt double %f2, %f3
174 br i1 %cmp, label %if.else, label %if.then 186 br i1 %cmp, label %if.else, label %if.then
175 187
176 if.then: ; preds = %entry 188 if.then: ; preds = %entry