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comparison test/CodeGen/Mips/mips64extins.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s 1 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s
2 2
3 define i64 @dext(i64 %i) nounwind readnone { 3 define i64 @dext(i64 %i) nounwind readnone {
4 entry: 4 entry:
5 ; CHECK-LABEL: dext:
5 ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10 6 ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
6 %shr = lshr i64 %i, 5 7 %shr = lshr i64 %i, 5
7 %and = and i64 %shr, 1023 8 %and = and i64 %shr, 1023
8 ret i64 %and 9 ret i64 %and
9 } 10 }
10 11
11 define i64 @dextm(i64 %i) nounwind readnone { 12 define i64 @dextm(i64 %i) nounwind readnone {
12 entry: 13 entry:
13 ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 14 ; CHECK-LABEL: dextm:
15 ; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
14 %shr = lshr i64 %i, 5 16 %shr = lshr i64 %i, 5
15 %and = and i64 %shr, 17179869183 17 %and = and i64 %shr, 17179869183
16 ret i64 %and 18 ret i64 %and
17 } 19 }
18 20
19 define i64 @dextu(i64 %i) nounwind readnone { 21 define i64 @dextu(i64 %i) nounwind readnone {
20 entry: 22 entry:
21 ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 23 ; CHECK-LABEL: dextu:
24 ; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
22 %shr = lshr i64 %i, 34 25 %shr = lshr i64 %i, 34
23 %and = and i64 %shr, 63 26 %and = and i64 %shr, 63
24 ret i64 %and 27 ret i64 %and
25 } 28 }
26 29
27 define i64 @dins(i64 %i, i64 %j) nounwind readnone { 30 define i64 @dins(i64 %i, i64 %j) nounwind readnone {
28 entry: 31 entry:
32 ; CHECK-LABEL: dins:
29 ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10 33 ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
30 %shl2 = shl i64 %j, 8 34 %shl2 = shl i64 %j, 8
31 %and = and i64 %shl2, 261888 35 %and = and i64 %shl2, 261888
32 %and3 = and i64 %i, -261889 36 %and3 = and i64 %i, -261889
33 %or = or i64 %and3, %and 37 %or = or i64 %and3, %and
34 ret i64 %or 38 ret i64 %or
35 } 39 }
36 40
37 define i64 @dinsm(i64 %i, i64 %j) nounwind readnone { 41 define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
38 entry: 42 entry:
43 ; CHECK-LABEL: dinsm:
39 ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 44 ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33
40 %shl4 = shl i64 %j, 10 45 %shl4 = shl i64 %j, 10
41 %and = and i64 %shl4, 8796093021184 46 %and = and i64 %shl4, 8796093021184
42 %and5 = and i64 %i, -8796093021185 47 %and5 = and i64 %i, -8796093021185
43 %or = or i64 %and5, %and 48 %or = or i64 %and5, %and
44 ret i64 %or 49 ret i64 %or
45 } 50 }
46 51
47 define i64 @dinsu(i64 %i, i64 %j) nounwind readnone { 52 define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
48 entry: 53 entry:
54 ; CHECK-LABEL: dinsu:
49 ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 55 ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
50 %shl4 = shl i64 %j, 40 56 %shl4 = shl i64 %j, 40
51 %and = and i64 %shl4, 9006099743113216 57 %and = and i64 %shl4, 9006099743113216
52 %and5 = and i64 %i, -9006099743113217 58 %and5 = and i64 %i, -9006099743113217
53 %or = or i64 %and5, %and 59 %or = or i64 %and5, %and