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comparison test/CodeGen/Mips/mips64shift.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s 1 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s
2 ; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s
2 3
3 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { 4 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
4 entry: 5 entry:
5 ; CHECK: dsllv 6 ; ALL: dsllv
6 %shl = shl i64 %a0, %a1 7 %shl = shl i64 %a0, %a1
7 ret i64 %shl 8 ret i64 %shl
8 } 9 }
9 10
10 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { 11 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
11 entry: 12 entry:
12 ; CHECK: dsrav 13 ; ALL: dsrav
13 %shr = ashr i64 %a0, %a1 14 %shr = ashr i64 %a0, %a1
14 ret i64 %shr 15 ret i64 %shr
15 } 16 }
16 17
17 define i64 @f2(i64 %a0, i64 %a1) nounwind readnone { 18 define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
18 entry: 19 entry:
19 ; CHECK: dsrlv 20 ; ALL: dsrlv
20 %shr = lshr i64 %a0, %a1 21 %shr = lshr i64 %a0, %a1
21 ret i64 %shr 22 ret i64 %shr
22 } 23 }
23 24
24 define i64 @f3(i64 %a0) nounwind readnone { 25 define i64 @f3(i64 %a0) nounwind readnone {
25 entry: 26 entry:
26 ; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10 27 ; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
27 %shl = shl i64 %a0, 10 28 %shl = shl i64 %a0, 10
28 ret i64 %shl 29 ret i64 %shl
29 } 30 }
30 31
31 define i64 @f4(i64 %a0) nounwind readnone { 32 define i64 @f4(i64 %a0) nounwind readnone {
32 entry: 33 entry:
33 ; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10 34 ; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
34 %shr = ashr i64 %a0, 10 35 %shr = ashr i64 %a0, 10
35 ret i64 %shr 36 ret i64 %shr
36 } 37 }
37 38
38 define i64 @f5(i64 %a0) nounwind readnone { 39 define i64 @f5(i64 %a0) nounwind readnone {
39 entry: 40 entry:
40 ; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10 41 ; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
41 %shr = lshr i64 %a0, 10 42 %shr = lshr i64 %a0, 10
42 ret i64 %shr 43 ret i64 %shr
43 } 44 }
44 45
45 define i64 @f6(i64 %a0) nounwind readnone { 46 define i64 @f6(i64 %a0) nounwind readnone {
46 entry: 47 entry:
47 ; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 48 ; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
48 %shl = shl i64 %a0, 40 49 %shl = shl i64 %a0, 40
49 ret i64 %shl 50 ret i64 %shl
50 } 51 }
51 52
52 define i64 @f7(i64 %a0) nounwind readnone { 53 define i64 @f7(i64 %a0) nounwind readnone {
53 entry: 54 entry:
54 ; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 55 ; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
55 %shr = ashr i64 %a0, 40 56 %shr = ashr i64 %a0, 40
56 ret i64 %shr 57 ret i64 %shr
57 } 58 }
58 59
59 define i64 @f8(i64 %a0) nounwind readnone { 60 define i64 @f8(i64 %a0) nounwind readnone {
60 entry: 61 entry:
61 ; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 62 ; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
62 %shr = lshr i64 %a0, 40 63 %shr = lshr i64 %a0, 40
63 ret i64 %shr 64 ret i64 %shr
64 } 65 }
65 66
66 define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { 67 define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
67 entry: 68 entry:
68 ; CHECK-NOT: sll 69 ; CHECK-NOT: sll
69 ; CHECK: drotrv 70 ; ALL: drotrv
70 %shr = lshr i64 %a0, %a1 71 %shr = lshr i64 %a0, %a1
71 %sub = sub i64 64, %a1 72 %sub = sub i64 64, %a1
72 %shl = shl i64 %a0, %sub 73 %shl = shl i64 %a0, %sub
73 %or = or i64 %shl, %shr 74 %or = or i64 %shl, %shr
74 ret i64 %or 75 ret i64 %or
75 } 76 }
76 77
77 define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { 78 define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
78 entry: 79 entry:
79 ; CHECK-NOT: sll 80 ; CHECK-NOT: sll
80 ; CHECK: drotrv 81 ; ALL: drotrv
81 %shl = shl i64 %a0, %a1 82 %shl = shl i64 %a0, %a1
82 %sub = sub i64 64, %a1 83 %sub = sub i64 64, %a1
83 %shr = lshr i64 %a0, %sub 84 %shr = lshr i64 %a0, %sub
84 %or = or i64 %shr, %shl 85 %or = or i64 %shr, %shl
85 ret i64 %or 86 ret i64 %or
86 } 87 }
87 88
88 define i64 @f11(i64 %a0) nounwind readnone { 89 define i64 @f11(i64 %a0) nounwind readnone {
89 entry: 90 entry:
90 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 91 ; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
91 %shr = lshr i64 %a0, 10 92 %shr = lshr i64 %a0, 10
92 %shl = shl i64 %a0, 54 93 %shl = shl i64 %a0, 54
93 %or = or i64 %shr, %shl 94 %or = or i64 %shr, %shl
94 ret i64 %or 95 ret i64 %or
95 } 96 }
96 97
97 define i64 @f12(i64 %a0) nounwind readnone { 98 define i64 @f12(i64 %a0) nounwind readnone {
98 entry: 99 entry:
99 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 100 ; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
100 %shl = shl i64 %a0, 10 101 %shl = shl i64 %a0, 10
101 %shr = lshr i64 %a0, 54 102 %shr = lshr i64 %a0, 54
102 %or = or i64 %shl, %shr 103 %or = or i64 %shl, %shr
103 ret i64 %or 104 ret i64 %or
104 } 105 }