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comparison lib/MC/MCSubtargetInfo.cpp @ 77:54457678186b

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
15 #include "llvm/Support/raw_ostream.h" 15 #include "llvm/Support/raw_ostream.h"
16 #include <algorithm> 16 #include <algorithm>
17 17
18 using namespace llvm; 18 using namespace llvm;
19 19
20 MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
21
22 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented 20 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
23 /// with feature string). Recompute feature bits and scheduling model. 21 /// with feature string). Recompute feature bits and scheduling model.
24 void 22 void
25 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) { 23 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
26 SubtargetFeatures Features(FS); 24 SubtargetFeatures Features(FS);
27 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, 25 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
28 ProcFeatures, NumFeatures);
29
30 InitCPUSchedModel(CPU); 26 InitCPUSchedModel(CPU);
31 } 27 }
32 28
33 void 29 void
34 MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) { 30 MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
35 if (!CPU.empty()) 31 if (!CPU.empty())
36 CPUSchedModel = getSchedModelForCPU(CPU); 32 CPUSchedModel = getSchedModelForCPU(CPU);
37 else 33 else
38 CPUSchedModel = &MCSchedModel::DefaultSchedModel; 34 CPUSchedModel = MCSchedModel::GetDefaultSchedModel();
39 } 35 }
40 36
41 void 37 void
42 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, 38 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
43 const SubtargetFeatureKV *PF, 39 ArrayRef<SubtargetFeatureKV> PF,
44 const SubtargetFeatureKV *PD, 40 ArrayRef<SubtargetFeatureKV> PD,
45 const SubtargetInfoKV *ProcSched, 41 const SubtargetInfoKV *ProcSched,
46 const MCWriteProcResEntry *WPR, 42 const MCWriteProcResEntry *WPR,
47 const MCWriteLatencyEntry *WL, 43 const MCWriteLatencyEntry *WL,
48 const MCReadAdvanceEntry *RA, 44 const MCReadAdvanceEntry *RA,
49 const InstrStage *IS, 45 const InstrStage *IS,
50 const unsigned *OC, 46 const unsigned *OC,
51 const unsigned *FP, 47 const unsigned *FP) {
52 unsigned NF, unsigned NP) {
53 TargetTriple = TT; 48 TargetTriple = TT;
54 ProcFeatures = PF; 49 ProcFeatures = PF;
55 ProcDesc = PD; 50 ProcDesc = PD;
56 ProcSchedModels = ProcSched; 51 ProcSchedModels = ProcSched;
57 WriteProcResTable = WPR; 52 WriteProcResTable = WPR;
59 ReadAdvanceTable = RA; 54 ReadAdvanceTable = RA;
60 55
61 Stages = IS; 56 Stages = IS;
62 OperandCycles = OC; 57 OperandCycles = OC;
63 ForwardingPaths = FP; 58 ForwardingPaths = FP;
64 NumFeatures = NF;
65 NumProcs = NP;
66 59
67 InitMCProcessorInfo(CPU, FS); 60 InitMCProcessorInfo(CPU, FS);
68 } 61 }
69 62
70 /// ToggleFeature - Toggle a feature and returns the re-computed feature 63 /// ToggleFeature - Toggle a feature and returns the re-computed feature
76 69
77 /// ToggleFeature - Toggle a feature and returns the re-computed feature 70 /// ToggleFeature - Toggle a feature and returns the re-computed feature
78 /// bits. This version will also change all implied bits. 71 /// bits. This version will also change all implied bits.
79 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { 72 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
80 SubtargetFeatures Features; 73 SubtargetFeatures Features;
81 FeatureBits = Features.ToggleFeature(FeatureBits, FS, 74 FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
82 ProcFeatures, NumFeatures);
83 return FeatureBits; 75 return FeatureBits;
84 } 76 }
85 77
86 78
87 const MCSchedModel * 79 MCSchedModel
88 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { 80 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
89 assert(ProcSchedModels && "Processor machine model not available!"); 81 assert(ProcSchedModels && "Processor machine model not available!");
90 82
83 unsigned NumProcs = ProcDesc.size();
91 #ifndef NDEBUG 84 #ifndef NDEBUG
92 for (size_t i = 1; i < NumProcs; i++) { 85 for (size_t i = 1; i < NumProcs; i++) {
93 assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 && 86 assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
94 "Processor machine model table is not sorted"); 87 "Processor machine model table is not sorted");
95 } 88 }
100 std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU); 93 std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
101 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) { 94 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
102 errs() << "'" << CPU 95 errs() << "'" << CPU
103 << "' is not a recognized processor for this target" 96 << "' is not a recognized processor for this target"
104 << " (ignoring processor)\n"; 97 << " (ignoring processor)\n";
105 return &MCSchedModel::DefaultSchedModel; 98 return MCSchedModel::GetDefaultSchedModel();
106 } 99 }
107 assert(Found->Value && "Missing processor SchedModel value"); 100 assert(Found->Value && "Missing processor SchedModel value");
108 return (const MCSchedModel *)Found->Value; 101 return *(const MCSchedModel *)Found->Value;
109 } 102 }
110 103
111 InstrItineraryData 104 InstrItineraryData
112 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const { 105 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
113 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU); 106 const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
114 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); 107 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
115 } 108 }
116 109
117 /// Initialize an InstrItineraryData instance. 110 /// Initialize an InstrItineraryData instance.
118 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { 111 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {