Members/tobaru/cbc/CbC_llvm: lib/Target/SystemZ/SystemZInstrFormats.td comparison

comparison lib/Target/SystemZ/SystemZInstrFormats.td @ 77:54457678186b

LLVM 3.6

author	Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date	Mon, 08 Sep 2014 22:06:00 +0900
parents	95c75e76d11b
children	afa8332a0e37

comparison

equal deleted inserted replaced

-:e874dbf0ad9d
+:54457678186b
 //     The instruction stores a range of registers to the address,
 //     with the explicit operands giving the first and last register
 //     to store.  Other stored registers are added as implicit uses.
 //
 //   Unary:
-//     One register output operand and one input operand.  The input
+//     One register output operand and one input operand.
-//     operand may be a register, immediate or memory.
 //
 //   Binary:
-//     One register output operand and two input operands.  The first
+//     One register output operand and two input operands.
-//     input operand is always a register and he second may be a register,
-//     immediate or memory.
-//
-//   Shift:
-//     One register output operand and two input operands.  The first
-//     input operand is a register and the second has the same form as
-//     an address (although it isn't actually used to address memory).
 //
 //   Compare:
-//     Two input operands.  The first operand is always a register,
+//     Two input operands and an implicit CC output operand.
-//     the second may be a register, immediate or memory.
 //
 //   Ternary:
-//     One register output operand and three register input operands.
+//     One register output operand and three input operands.
+//
+//   LoadAndOp:
+//     One output operand and two input operands, one of which is an address.
+//     The instruction both reads from and writes to the address.
 //
 //   CmpSwap:
-//     One output operand and three input operands.  The first two
+//     One output operand and three input operands, one of which is an address.
-//     operands are registers and the third is an address.  The instruction
+//     The instruction both reads from and writes to the address.
-//     both reads from and writes to the address.
 //
 //   RotateSelect:
 //     One output operand and five input operands.  The first two operands
 //     are registers and the other three are immediates.
 //
 // Like CondStoreRSY, but used for the raw assembly form.  The condition-code
 // mask is the third operand rather than being part of the mnemonic.
 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
 RegisterOperand cls, bits<5> bytes,
 AddressingMode mode = bdaddr20only>
-: InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, uimm8zx4:$R3),
+: InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$R3),
 mnemonic#"\t$R1, $BD2, $R3", []>,
 Requires<[FeatureLoadStoreOnCond]> {
 let mayStore = 1;
 let AccessBytes = bytes;
 }
 let OpType = "reg";
 }
 class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
 RegisterOperand cls2>
-: InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2),
+: InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2),
 mnemonic#"r\t$R1, $R3, $R2", []> {
 let OpKey = mnemonic ## cls1;
 let OpType = "reg";
 let R4 = 0;
 }
 class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
 RegisterOperand cls2>
-: InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2, uimm8zx4:$R4),
+: InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4),
 mnemonic#"\t$R1, $R3, $R2, $R4", []>;
 // These instructions are generated by if conversion.  The old value of R1
 // is added as an implicit use.
 class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
 // Like CondUnaryRRF, but used for the raw assembly form.  The condition-code
 // mask is the third operand rather than being part of the mnemonic.
 class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
 RegisterOperand cls2>
-: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, uimm8zx4:$R3),
+: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3),
 mnemonic#"r\t$R1, $R2, $R3", []>,
 Requires<[FeatureLoadStoreOnCond]> {
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
 let R4 = 0;
 // Like CondUnaryRSY, but used for the raw assembly form.  The condition-code
 // mask is the third operand rather than being part of the mnemonic.
 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
 RegisterOperand cls, bits<5> bytes,
 AddressingMode mode = bdaddr20only>
-: InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, uimm8zx4:$R3),
+: InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$R3),
 mnemonic#"\t$R1, $BD2, $R3", []>,
 Requires<[FeatureLoadStoreOnCond]> {
 let mayLoad = 1;
 let AccessBytes = bytes;
 let Constraints = "$R1 = $R1src";
 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
 mnemonic#"\t$R1, $I2",
 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
+}
+class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
+RegisterOperand cls>
+: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
+mnemonic#"\t$R1, $BD2",
+[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
+let R3 = 0;
+let Constraints = "$R1 = $R1src";
+let DisableEncoding = "$R1src";
+}
+class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+RegisterOperand cls>
+: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
+mnemonic#"\t$R1, $R3, $BD2",
+[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
+multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
+SDPatternOperator operator, RegisterOperand cls> {
+let NumOpsKey = mnemonic in {
+let NumOpsValue = "3" in
+def K  : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
+Requires<[FeatureDistinctOps]>;
+let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
+def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
+}
 }
 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
 AddressingMode mode = bdxaddr12only>
 let DispSize = "20" in
 def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
 }
 }
-class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
-RegisterOperand cls>
-: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
-mnemonic#"\t$R1, $BD2",
-[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
-let R3 = 0;
-let Constraints = "$R1 = $R1src";
-let DisableEncoding = "$R1src";
-}
-class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
-RegisterOperand cls>
-: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
-mnemonic#"\t$R1, $R3, $BD2",
-[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
-multiclass ShiftRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
-SDPatternOperator operator, RegisterOperand cls> {
-let NumOpsKey = mnemonic in {
-let NumOpsValue = "3" in
-def K  : ShiftRSY<mnemonic##"k", opcode2, null_frag, cls>,
-Requires<[FeatureDistinctOps]>;
-let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
-def "" : ShiftRS<mnemonic, opcode1, operator, cls>;
-}
-}
 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
 RegisterOperand cls1, RegisterOperand cls2>
 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
 mnemonic#"r\t$R1, $R2",
 [(operator cls1:$R1, cls2:$R2)]> {
 let DisableEncoding = "$R1src";
 let mayLoad = 1;
 let AccessBytes = bytes;
 }
+class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+RegisterOperand cls, AddressingMode mode = bdaddr20only>
+: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
+mnemonic#"\t$R1, $R3, $BD2",
+[(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
+let mayLoad = 1;
+let mayStore = 1;
+}
 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
 RegisterOperand cls, AddressingMode mode = bdaddr12only>
 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
 mnemonic#"\t$R1, $R3, $BD2",
 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
 }
 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
 RegisterOperand cls2>
 : InstRIEf<opcode, (outs cls1:$R1),
-(ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5),
+(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
+imm32zx6:$I5),
 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
 }
 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
-: InstRXY<opcode, (outs), (ins uimm8zx4:$R1, bdxaddr20only:$XBD2),
+: InstRXY<opcode, (outs), (ins imm32zx4:$R1, bdxaddr20only:$XBD2),
 mnemonic##"\t$R1, $XBD2",
-[(operator uimm8zx4:$R1, bdxaddr20only:$XBD2)]>;
+[(operator imm32zx4:$R1, bdxaddr20only:$XBD2)]>;
 class PrefetchRILPC<string mnemonic, bits<12> opcode,
 SDPatternOperator operator>
-: InstRIL<opcode, (outs), (ins uimm8zx4:$R1, pcrel32:$I2),
+: InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2),
 mnemonic##"\t$R1, $I2",
-[(operator uimm8zx4:$R1, pcrel32:$I2)]> {
+[(operator imm32zx4:$R1, pcrel32:$I2)]> {
 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
 // However, BDXs have two extra operands and are therefore 6 units more
 // complex.
 let AddedComplexity = 7;
 }
 // Like RotateSelectRIEf, but expanded after RA depending on the choice
 // of registers.
 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
 : Pseudo<(outs cls1:$R1),
-(ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5),
+(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
+imm32zx6:$I5),
 []> {
 let Constraints = "$R1 = $R1src";
 let DisableEncoding = "$R1src";
 }
 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
 // the value of the PSW's 2-bit condition code field.
 class SelectWrapper<RegisterOperand cls>
 : Pseudo<(outs cls:$dst),
-(ins cls:$src1, cls:$src2, uimm8zx4:$valid, uimm8zx4:$cc),
+(ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
-uimm8zx4:$valid, uimm8zx4:$cc))]> {
+imm32zx4:$valid, imm32zx4:$cc))]> {
 let usesCustomInserter = 1;
 // Although the instructions used by these nodes do not in themselves
 // change CC, the insertion requires new blocks, and CC cannot be live
 // across them.
 let Defs = [CC];
 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
 SDPatternOperator load, AddressingMode mode> {
 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
 def "" : Pseudo<(outs),
-(ins cls:$new, mode:$addr, uimm8zx4:$valid, uimm8zx4:$cc),
+(ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
 [(store (z_select_ccmask cls:$new, (load mode:$addr),
-uimm8zx4:$valid, uimm8zx4:$cc),
+imm32zx4:$valid, imm32zx4:$cc),
 mode:$addr)]>;
 def Inv : Pseudo<(outs),
-(ins cls:$new, mode:$addr, uimm8zx4:$valid, uimm8zx4:$cc),
+(ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
 [(store (z_select_ccmask (load mode:$addr), cls:$new,
-uimm8zx4:$valid, uimm8zx4:$cc),
+imm32zx4:$valid, imm32zx4:$cc),
 mode:$addr)]>;
 }
 }
 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation.  PAT and OPERAND
 }
 // An alias of a RotateSelectRIEf, but with different register sizes.
 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
 : Alias<6, (outs cls1:$R1),
-(ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5), []> {
+(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
-let Constraints = "$R1 = $R1src";
+imm32zx6:$I5), []> {
-}
+let Constraints = "$R1 = $R1src";
+}

Mercurial > hg > Members > tobaru > cbc > CbC_llvm

comparison lib/Target/SystemZ/SystemZInstrFormats.td @ 77:54457678186b