Mercurial > hg > Members > tobaru > cbc > CbC_llvm
comparison lib/Target/X86/X86InstrCMovSetCC.td @ 77:54457678186b
LLVM 3.6
author | Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> |
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date | Mon, 08 Sep 2014 22:06:00 +0900 |
parents | 95c75e76d11b |
children | afa8332a0e37 |
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34:e874dbf0ad9d | 77:54457678186b |
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20 def NAME#16rr | 20 def NAME#16rr |
21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), | 21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
22 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), | 22 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), |
23 [(set GR16:$dst, | 23 [(set GR16:$dst, |
24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))], | 24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))], |
25 IIC_CMOV16_RR>,TB,OpSize; | 25 IIC_CMOV16_RR>, TB, OpSize16; |
26 def NAME#32rr | 26 def NAME#32rr |
27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), | 27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
28 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), | 28 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), |
29 [(set GR32:$dst, | 29 [(set GR32:$dst, |
30 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))], | 30 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))], |
31 IIC_CMOV32_RR>, TB; | 31 IIC_CMOV32_RR>, TB, OpSize32; |
32 def NAME#64rr | 32 def NAME#64rr |
33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), | 33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
34 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), | 34 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), |
35 [(set GR64:$dst, | 35 [(set GR64:$dst, |
36 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))], | 36 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))], |
42 def NAME#16rm | 42 def NAME#16rm |
43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), | 43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
44 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), | 44 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), |
45 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), | 45 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
46 CondNode, EFLAGS))], IIC_CMOV16_RM>, | 46 CondNode, EFLAGS))], IIC_CMOV16_RM>, |
47 TB, OpSize; | 47 TB, OpSize16; |
48 def NAME#32rm | 48 def NAME#32rm |
49 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), | 49 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
50 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), | 50 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), |
51 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), | 51 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
52 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB; | 52 CondNode, EFLAGS))], IIC_CMOV32_RM>, |
53 TB, OpSize32; | |
53 def NAME#64rm | 54 def NAME#64rm |
54 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), | 55 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
55 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), | 56 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), |
56 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), | 57 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
57 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB; | 58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB; |
79 | 80 |
80 | 81 |
81 // SetCC instructions. | 82 // SetCC instructions. |
82 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> { | 83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> { |
83 let Uses = [EFLAGS] in { | 84 let Uses = [EFLAGS] in { |
84 def r : I<opc, MRM0r, (outs GR8:$dst), (ins), | 85 def r : I<opc, MRMXr, (outs GR8:$dst), (ins), |
85 !strconcat(Mnemonic, "\t$dst"), | 86 !strconcat(Mnemonic, "\t$dst"), |
86 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))], | 87 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))], |
87 IIC_SET_R>, TB, Sched<[WriteALU]>; | 88 IIC_SET_R>, TB, Sched<[WriteALU]>; |
88 def m : I<opc, MRM0m, (outs), (ins i8mem:$dst), | 89 def m : I<opc, MRMXm, (outs), (ins i8mem:$dst), |
89 !strconcat(Mnemonic, "\t$dst"), | 90 !strconcat(Mnemonic, "\t$dst"), |
90 [(store (X86setcc OpNode, EFLAGS), addr:$dst)], | 91 [(store (X86setcc OpNode, EFLAGS), addr:$dst)], |
91 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>; | 92 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>; |
92 } // Uses = [EFLAGS] | 93 } // Uses = [EFLAGS] |
93 } | 94 } |