Mercurial > hg > Members > tobaru > cbc > CbC_llvm

comparison lib/Target/X86/X86InstrShiftRotate.td @ 77:54457678186b

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), 20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 "shl{b}\t{%cl, $dst|$dst, cl}", 21 "shl{b}\t{%cl, $dst|$dst, cl}",
22 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>; 22 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1), 23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 "shl{w}\t{%cl, $dst|$dst, cl}", 24 "shl{w}\t{%cl, $dst|$dst, cl}",
25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize; 25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), 26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 "shl{l}\t{%cl, $dst|$dst, cl}", 27 "shl{l}\t{%cl, $dst|$dst, cl}",
28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>; 28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), 29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 "shl{q}\t{%cl, $dst|$dst, cl}", 30 "shl{q}\t{%cl, $dst|$dst, cl}",
31 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>; 31 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
32 } // Uses = [CL] 32 } // Uses = [CL]
33 33
37 37
38 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. 38 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
40 "shl{w}\t{$src2, $dst|$dst, $src2}", 40 "shl{w}\t{$src2, $dst|$dst, $src2}",
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>, 41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
42 OpSize; 42 OpSize16;
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
44 "shl{l}\t{$src2, $dst|$dst, $src2}", 44 "shl{l}\t{$src2, $dst|$dst, $src2}",
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>; 45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
46 OpSize32;
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), 47 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
47 (ins GR64:$src1, i8imm:$src2), 48 (ins GR64:$src1, i8imm:$src2),
48 "shl{q}\t{$src2, $dst|$dst, $src2}", 49 "shl{q}\t{$src2, $dst|$dst, $src2}",
49 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))], 50 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
50 IIC_SR>; 51 IIC_SR>;
53 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one). 54 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
54 let hasSideEffects = 0 in { 55 let hasSideEffects = 0 in {
55 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), 56 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
56 "shl{b}\t$dst", [], IIC_SR>; 57 "shl{b}\t$dst", [], IIC_SR>;
57 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), 58 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
58 "shl{w}\t$dst", [], IIC_SR>, OpSize; 59 "shl{w}\t$dst", [], IIC_SR>, OpSize16;
59 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), 60 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
60 "shl{l}\t$dst", [], IIC_SR>; 61 "shl{l}\t$dst", [], IIC_SR>, OpSize32;
61 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), 62 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
62 "shl{q}\t$dst", [], IIC_SR>; 63 "shl{q}\t$dst", [], IIC_SR>;
63 } // hasSideEffects = 0 64 } // hasSideEffects = 0
64 } // isConvertibleToThreeAddress = 1 65 } // isConvertibleToThreeAddress = 1
65 } // Constraints = "$src = $dst", SchedRW 66 } // Constraints = "$src = $dst", SchedRW
73 "shl{b}\t{%cl, $dst|$dst, cl}", 74 "shl{b}\t{%cl, $dst|$dst, cl}",
74 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>; 75 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
75 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), 76 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
76 "shl{w}\t{%cl, $dst|$dst, cl}", 77 "shl{w}\t{%cl, $dst|$dst, cl}",
77 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>, 78 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
78 OpSize; 79 OpSize16;
79 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), 80 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
80 "shl{l}\t{%cl, $dst|$dst, cl}", 81 "shl{l}\t{%cl, $dst|$dst, cl}",
81 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>; 82 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
83 OpSize32;
82 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), 84 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
83 "shl{q}\t{%cl, $dst|$dst, cl}", 85 "shl{q}\t{%cl, $dst|$dst, cl}",
84 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>; 86 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
85 } 87 }
86 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), 88 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
88 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], 90 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
89 IIC_SR>; 91 IIC_SR>;
90 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), 92 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
91 "shl{w}\t{$src, $dst|$dst, $src}", 93 "shl{w}\t{$src, $dst|$dst, $src}",
92 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], 94 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
93 IIC_SR>, 95 IIC_SR>, OpSize16;
94 OpSize;
95 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), 96 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
96 "shl{l}\t{$src, $dst|$dst, $src}", 97 "shl{l}\t{$src, $dst|$dst, $src}",
97 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], 98 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
98 IIC_SR>; 99 IIC_SR>, OpSize32;
99 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src), 100 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
100 "shl{q}\t{$src, $dst|$dst, $src}", 101 "shl{q}\t{$src, $dst|$dst, $src}",
101 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], 102 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
102 IIC_SR>; 103 IIC_SR>;
103 104
107 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)], 108 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
108 IIC_SR>; 109 IIC_SR>;
109 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), 110 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
110 "shl{w}\t$dst", 111 "shl{w}\t$dst",
111 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)], 112 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
112 IIC_SR>, 113 IIC_SR>, OpSize16;
113 OpSize;
114 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), 114 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
115 "shl{l}\t$dst", 115 "shl{l}\t$dst",
116 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)], 116 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
117 IIC_SR>; 117 IIC_SR>, OpSize32;
118 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), 118 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
119 "shl{q}\t$dst", 119 "shl{q}\t$dst",
120 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)], 120 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
121 IIC_SR>; 121 IIC_SR>;
122 } // SchedRW 122 } // SchedRW
126 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), 126 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
127 "shr{b}\t{%cl, $dst|$dst, cl}", 127 "shr{b}\t{%cl, $dst|$dst, cl}",
128 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>; 128 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
129 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1), 129 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
130 "shr{w}\t{%cl, $dst|$dst, cl}", 130 "shr{w}\t{%cl, $dst|$dst, cl}",
131 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize; 131 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
132 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1), 132 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
133 "shr{l}\t{%cl, $dst|$dst, cl}", 133 "shr{l}\t{%cl, $dst|$dst, cl}",
134 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>; 134 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
135 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), 135 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
136 "shr{q}\t{%cl, $dst|$dst, cl}", 136 "shr{q}\t{%cl, $dst|$dst, cl}",
137 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>; 137 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
138 } 138 }
139 139
141 "shr{b}\t{$src2, $dst|$dst, $src2}", 141 "shr{b}\t{$src2, $dst|$dst, $src2}",
142 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>; 142 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
143 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 143 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
144 "shr{w}\t{$src2, $dst|$dst, $src2}", 144 "shr{w}\t{$src2, $dst|$dst, $src2}",
145 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))], 145 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
146 IIC_SR>, OpSize; 146 IIC_SR>, OpSize16;
147 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 147 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
148 "shr{l}\t{$src2, $dst|$dst, $src2}", 148 "shr{l}\t{$src2, $dst|$dst, $src2}",
149 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))], 149 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
150 IIC_SR>; 150 IIC_SR>, OpSize32;
151 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), 151 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
152 "shr{q}\t{$src2, $dst|$dst, $src2}", 152 "shr{q}\t{$src2, $dst|$dst, $src2}",
153 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>; 153 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
154 154
155 // Shift right by 1 155 // Shift right by 1
156 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), 156 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
157 "shr{b}\t$dst", 157 "shr{b}\t$dst",
158 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>; 158 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
159 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), 159 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
160 "shr{w}\t$dst", 160 "shr{w}\t$dst",
161 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize; 161 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
162 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), 162 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
163 "shr{l}\t$dst", 163 "shr{l}\t$dst",
164 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>; 164 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
165 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), 165 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
166 "shr{q}\t$dst", 166 "shr{q}\t$dst",
167 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>; 167 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
168 } // Constraints = "$src = $dst", SchedRW 168 } // Constraints = "$src = $dst", SchedRW
169 169
174 "shr{b}\t{%cl, $dst|$dst, cl}", 174 "shr{b}\t{%cl, $dst|$dst, cl}",
175 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>; 175 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
176 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), 176 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
177 "shr{w}\t{%cl, $dst|$dst, cl}", 177 "shr{w}\t{%cl, $dst|$dst, cl}",
178 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>, 178 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
179 OpSize; 179 OpSize16;
180 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), 180 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
181 "shr{l}\t{%cl, $dst|$dst, cl}", 181 "shr{l}\t{%cl, $dst|$dst, cl}",
182 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>; 182 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
183 OpSize32;
183 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), 184 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
184 "shr{q}\t{%cl, $dst|$dst, cl}", 185 "shr{q}\t{%cl, $dst|$dst, cl}",
185 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>; 186 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
186 } 187 }
187 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), 188 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
189 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], 190 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
190 IIC_SR>; 191 IIC_SR>;
191 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), 192 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
192 "shr{w}\t{$src, $dst|$dst, $src}", 193 "shr{w}\t{$src, $dst|$dst, $src}",
193 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], 194 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
194 IIC_SR>, 195 IIC_SR>, OpSize16;
195 OpSize;
196 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), 196 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
197 "shr{l}\t{$src, $dst|$dst, $src}", 197 "shr{l}\t{$src, $dst|$dst, $src}",
198 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], 198 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
199 IIC_SR>; 199 IIC_SR>, OpSize32;
200 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src), 200 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
201 "shr{q}\t{$src, $dst|$dst, $src}", 201 "shr{q}\t{$src, $dst|$dst, $src}",
202 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], 202 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
203 IIC_SR>; 203 IIC_SR>;
204 204
208 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)], 208 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
209 IIC_SR>; 209 IIC_SR>;
210 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), 210 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
211 "shr{w}\t$dst", 211 "shr{w}\t$dst",
212 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)], 212 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
213 IIC_SR>,OpSize; 213 IIC_SR>, OpSize16;
214 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), 214 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
215 "shr{l}\t$dst", 215 "shr{l}\t$dst",
216 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)], 216 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
217 IIC_SR>; 217 IIC_SR>, OpSize32;
218 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), 218 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
219 "shr{q}\t$dst", 219 "shr{q}\t$dst",
220 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)], 220 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
221 IIC_SR>; 221 IIC_SR>;
222 } // SchedRW 222 } // SchedRW
228 [(set GR8:$dst, (sra GR8:$src1, CL))], 228 [(set GR8:$dst, (sra GR8:$src1, CL))],
229 IIC_SR>; 229 IIC_SR>;
230 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1), 230 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
231 "sar{w}\t{%cl, $dst|$dst, cl}", 231 "sar{w}\t{%cl, $dst|$dst, cl}",
232 [(set GR16:$dst, (sra GR16:$src1, CL))], 232 [(set GR16:$dst, (sra GR16:$src1, CL))],
233 IIC_SR>, OpSize; 233 IIC_SR>, OpSize16;
234 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1), 234 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
235 "sar{l}\t{%cl, $dst|$dst, cl}", 235 "sar{l}\t{%cl, $dst|$dst, cl}",
236 [(set GR32:$dst, (sra GR32:$src1, CL))], 236 [(set GR32:$dst, (sra GR32:$src1, CL))],
237 IIC_SR>; 237 IIC_SR>, OpSize32;
238 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), 238 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
239 "sar{q}\t{%cl, $dst|$dst, cl}", 239 "sar{q}\t{%cl, $dst|$dst, cl}",
240 [(set GR64:$dst, (sra GR64:$src1, CL))], 240 [(set GR64:$dst, (sra GR64:$src1, CL))],
241 IIC_SR>; 241 IIC_SR>;
242 } 242 }
246 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))], 246 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
247 IIC_SR>; 247 IIC_SR>;
248 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 248 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
249 "sar{w}\t{$src2, $dst|$dst, $src2}", 249 "sar{w}\t{$src2, $dst|$dst, $src2}",
250 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))], 250 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
251 IIC_SR>, 251 IIC_SR>, OpSize16;
252 OpSize;
253 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 252 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
254 "sar{l}\t{$src2, $dst|$dst, $src2}", 253 "sar{l}\t{$src2, $dst|$dst, $src2}",
255 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))], 254 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
256 IIC_SR>; 255 IIC_SR>, OpSize32;
257 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), 256 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
258 (ins GR64:$src1, i8imm:$src2), 257 (ins GR64:$src1, i8imm:$src2),
259 "sar{q}\t{$src2, $dst|$dst, $src2}", 258 "sar{q}\t{$src2, $dst|$dst, $src2}",
260 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))], 259 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
261 IIC_SR>; 260 IIC_SR>;
266 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))], 265 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
267 IIC_SR>; 266 IIC_SR>;
268 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), 267 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
269 "sar{w}\t$dst", 268 "sar{w}\t$dst",
270 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))], 269 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
271 IIC_SR>, OpSize; 270 IIC_SR>, OpSize16;
272 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), 271 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
273 "sar{l}\t$dst", 272 "sar{l}\t$dst",
274 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))], 273 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
275 IIC_SR>; 274 IIC_SR>, OpSize32;
276 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), 275 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
277 "sar{q}\t$dst", 276 "sar{q}\t$dst",
278 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))], 277 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
279 IIC_SR>; 278 IIC_SR>;
280 } // Constraints = "$src = $dst", SchedRW 279 } // Constraints = "$src = $dst", SchedRW
287 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)], 286 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
288 IIC_SR>; 287 IIC_SR>;
289 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), 288 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
290 "sar{w}\t{%cl, $dst|$dst, cl}", 289 "sar{w}\t{%cl, $dst|$dst, cl}",
291 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)], 290 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
292 IIC_SR>, OpSize; 291 IIC_SR>, OpSize16;
293 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), 292 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
294 "sar{l}\t{%cl, $dst|$dst, cl}", 293 "sar{l}\t{%cl, $dst|$dst, cl}",
295 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)], 294 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
296 IIC_SR>; 295 IIC_SR>, OpSize32;
297 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), 296 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
298 "sar{q}\t{%cl, $dst|$dst, cl}", 297 "sar{q}\t{%cl, $dst|$dst, cl}",
299 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)], 298 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
300 IIC_SR>; 299 IIC_SR>;
301 } 300 }
304 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], 303 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
305 IIC_SR>; 304 IIC_SR>;
306 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), 305 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
307 "sar{w}\t{$src, $dst|$dst, $src}", 306 "sar{w}\t{$src, $dst|$dst, $src}",
308 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], 307 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
309 IIC_SR>, 308 IIC_SR>, OpSize16;
310 OpSize;
311 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), 309 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
312 "sar{l}\t{$src, $dst|$dst, $src}", 310 "sar{l}\t{$src, $dst|$dst, $src}",
313 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], 311 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
314 IIC_SR>; 312 IIC_SR>, OpSize32;
315 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src), 313 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
316 "sar{q}\t{$src, $dst|$dst, $src}", 314 "sar{q}\t{$src, $dst|$dst, $src}",
317 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], 315 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
318 IIC_SR>; 316 IIC_SR>;
319 317
323 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)], 321 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
324 IIC_SR>; 322 IIC_SR>;
325 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), 323 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
326 "sar{w}\t$dst", 324 "sar{w}\t$dst",
327 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)], 325 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
328 IIC_SR>, 326 IIC_SR>, OpSize16;
329 OpSize;
330 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), 327 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
331 "sar{l}\t$dst", 328 "sar{l}\t$dst",
332 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)], 329 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
333 IIC_SR>; 330 IIC_SR>, OpSize32;
334 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), 331 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
335 "sar{q}\t$dst", 332 "sar{q}\t$dst",
336 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)], 333 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
337 IIC_SR>; 334 IIC_SR>;
338 } // SchedRW 335 } // SchedRW
350 let Uses = [CL] in 347 let Uses = [CL] in
351 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), 348 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
352 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 349 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
353 350
354 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), 351 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
355 "rcl{w}\t$dst", [], IIC_SR>, OpSize; 352 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
356 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), 353 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
357 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize; 354 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
358 let Uses = [CL] in 355 let Uses = [CL] in
359 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), 356 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
360 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize; 357 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
361 358
362 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), 359 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
363 "rcl{l}\t$dst", [], IIC_SR>; 360 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
364 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), 361 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
365 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 362 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
366 let Uses = [CL] in 363 let Uses = [CL] in
367 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), 364 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
368 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 365 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
369 366
370 367
371 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), 368 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
372 "rcl{q}\t$dst", [], IIC_SR>; 369 "rcl{q}\t$dst", [], IIC_SR>;
373 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt), 370 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
384 let Uses = [CL] in 381 let Uses = [CL] in
385 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), 382 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
386 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 383 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
387 384
388 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), 385 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
389 "rcr{w}\t$dst", [], IIC_SR>, OpSize; 386 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
390 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), 387 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
391 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize; 388 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
392 let Uses = [CL] in 389 let Uses = [CL] in
393 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), 390 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
394 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize; 391 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
395 392
396 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), 393 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
397 "rcr{l}\t$dst", [], IIC_SR>; 394 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
398 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), 395 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
399 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 396 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
400 let Uses = [CL] in 397 let Uses = [CL] in
401 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1), 398 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
402 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 399 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
403 400
404 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1), 401 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
405 "rcr{q}\t$dst", [], IIC_SR>; 402 "rcr{q}\t$dst", [], IIC_SR>;
406 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt), 403 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
407 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 404 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
415 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), 412 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
416 "rcl{b}\t$dst", [], IIC_SR>; 413 "rcl{b}\t$dst", [], IIC_SR>;
417 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt), 414 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
418 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 415 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
419 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), 416 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
420 "rcl{w}\t$dst", [], IIC_SR>, OpSize; 417 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
421 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt), 418 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
422 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize; 419 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
423 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), 420 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
424 "rcl{l}\t$dst", [], IIC_SR>; 421 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
425 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt), 422 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
426 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 423 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
427 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst), 424 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
428 "rcl{q}\t$dst", [], IIC_SR>; 425 "rcl{q}\t$dst", [], IIC_SR>;
429 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt), 426 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
430 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 427 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
431 428
432 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), 429 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
433 "rcr{b}\t$dst", [], IIC_SR>; 430 "rcr{b}\t$dst", [], IIC_SR>;
434 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt), 431 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
435 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 432 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
436 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), 433 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
437 "rcr{w}\t$dst", [], IIC_SR>, OpSize; 434 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
438 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt), 435 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
439 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize; 436 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
440 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), 437 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
441 "rcr{l}\t$dst", [], IIC_SR>; 438 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
442 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt), 439 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
443 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 440 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
444 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst), 441 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
445 "rcr{q}\t$dst", [], IIC_SR>; 442 "rcr{q}\t$dst", [], IIC_SR>;
446 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt), 443 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
447 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; 444 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
448 445
449 let Uses = [CL] in { 446 let Uses = [CL] in {
450 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), 447 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
451 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 448 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
452 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), 449 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
453 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize; 450 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
454 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst), 451 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
455 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 452 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
456 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst), 453 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
457 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 454 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
458 455
459 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst), 456 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
460 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 457 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
461 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst), 458 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
462 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize; 459 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
463 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst), 460 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
464 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 461 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
465 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), 462 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
466 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; 463 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
467 } 464 }
468 } // SchedRW 465 } // SchedRW
469 } // hasSideEffects = 0 466 } // hasSideEffects = 0
474 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), 471 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
475 "rol{b}\t{%cl, $dst|$dst, cl}", 472 "rol{b}\t{%cl, $dst|$dst, cl}",
476 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>; 473 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
477 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1), 474 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
478 "rol{w}\t{%cl, $dst|$dst, cl}", 475 "rol{w}\t{%cl, $dst|$dst, cl}",
479 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize; 476 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
480 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1), 477 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
481 "rol{l}\t{%cl, $dst|$dst, cl}", 478 "rol{l}\t{%cl, $dst|$dst, cl}",
482 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>; 479 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
483 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), 480 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
484 "rol{q}\t{%cl, $dst|$dst, cl}", 481 "rol{q}\t{%cl, $dst|$dst, cl}",
485 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>; 482 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
486 } 483 }
487 484
489 "rol{b}\t{$src2, $dst|$dst, $src2}", 486 "rol{b}\t{$src2, $dst|$dst, $src2}",
490 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>; 487 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
491 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 488 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
492 "rol{w}\t{$src2, $dst|$dst, $src2}", 489 "rol{w}\t{$src2, $dst|$dst, $src2}",
493 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))], 490 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
494 IIC_SR>, 491 IIC_SR>, OpSize16;
495 OpSize;
496 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 492 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
497 "rol{l}\t{$src2, $dst|$dst, $src2}", 493 "rol{l}\t{$src2, $dst|$dst, $src2}",
498 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))], 494 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
499 IIC_SR>; 495 IIC_SR>, OpSize32;
500 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), 496 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
501 (ins GR64:$src1, i8imm:$src2), 497 (ins GR64:$src1, i8imm:$src2),
502 "rol{q}\t{$src2, $dst|$dst, $src2}", 498 "rol{q}\t{$src2, $dst|$dst, $src2}",
503 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))], 499 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
504 IIC_SR>; 500 IIC_SR>;
509 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))], 505 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
510 IIC_SR>; 506 IIC_SR>;
511 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), 507 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
512 "rol{w}\t$dst", 508 "rol{w}\t$dst",
513 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))], 509 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
514 IIC_SR>, OpSize; 510 IIC_SR>, OpSize16;
515 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), 511 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
516 "rol{l}\t$dst", 512 "rol{l}\t$dst",
517 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))], 513 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
518 IIC_SR>; 514 IIC_SR>, OpSize32;
519 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), 515 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
520 "rol{q}\t$dst", 516 "rol{q}\t$dst",
521 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))], 517 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
522 IIC_SR>; 518 IIC_SR>;
523 } // Constraints = "$src = $dst", SchedRW 519 } // Constraints = "$src = $dst", SchedRW
529 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)], 525 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
530 IIC_SR>; 526 IIC_SR>;
531 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), 527 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
532 "rol{w}\t{%cl, $dst|$dst, cl}", 528 "rol{w}\t{%cl, $dst|$dst, cl}",
533 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)], 529 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
534 IIC_SR>, OpSize; 530 IIC_SR>, OpSize16;
535 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), 531 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
536 "rol{l}\t{%cl, $dst|$dst, cl}", 532 "rol{l}\t{%cl, $dst|$dst, cl}",
537 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)], 533 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
538 IIC_SR>; 534 IIC_SR>, OpSize32;
539 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), 535 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
540 "rol{q}\t{%cl, $dst|$dst, cl}", 536 "rol{q}\t{%cl, $dst|$dst, cl}",
541 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)], 537 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
542 IIC_SR>; 538 IIC_SR>;
543 } 539 }
546 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)], 542 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
547 IIC_SR>; 543 IIC_SR>;
548 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1), 544 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
549 "rol{w}\t{$src1, $dst|$dst, $src1}", 545 "rol{w}\t{$src1, $dst|$dst, $src1}",
550 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)], 546 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
551 IIC_SR>, 547 IIC_SR>, OpSize16;
552 OpSize;
553 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1), 548 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
554 "rol{l}\t{$src1, $dst|$dst, $src1}", 549 "rol{l}\t{$src1, $dst|$dst, $src1}",
555 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)], 550 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
556 IIC_SR>; 551 IIC_SR>, OpSize32;
557 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1), 552 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
558 "rol{q}\t{$src1, $dst|$dst, $src1}", 553 "rol{q}\t{$src1, $dst|$dst, $src1}",
559 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)], 554 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
560 IIC_SR>; 555 IIC_SR>;
561 556
565 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)], 560 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
566 IIC_SR>; 561 IIC_SR>;
567 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), 562 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
568 "rol{w}\t$dst", 563 "rol{w}\t$dst",
569 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)], 564 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
570 IIC_SR>, 565 IIC_SR>, OpSize16;
571 OpSize;
572 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), 566 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
573 "rol{l}\t$dst", 567 "rol{l}\t$dst",
574 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)], 568 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
575 IIC_SR>; 569 IIC_SR>, OpSize32;
576 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), 570 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
577 "rol{q}\t$dst", 571 "rol{q}\t$dst",
578 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)], 572 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
579 IIC_SR>; 573 IIC_SR>;
580 } // SchedRW 574 } // SchedRW
584 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), 578 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
585 "ror{b}\t{%cl, $dst|$dst, cl}", 579 "ror{b}\t{%cl, $dst|$dst, cl}",
586 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>; 580 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
587 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 581 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
588 "ror{w}\t{%cl, $dst|$dst, cl}", 582 "ror{w}\t{%cl, $dst|$dst, cl}",
589 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize; 583 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
590 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 584 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
591 "ror{l}\t{%cl, $dst|$dst, cl}", 585 "ror{l}\t{%cl, $dst|$dst, cl}",
592 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>; 586 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
593 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), 587 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
594 "ror{q}\t{%cl, $dst|$dst, cl}", 588 "ror{q}\t{%cl, $dst|$dst, cl}",
595 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>; 589 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
596 } 590 }
597 591
599 "ror{b}\t{$src2, $dst|$dst, $src2}", 593 "ror{b}\t{$src2, $dst|$dst, $src2}",
600 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>; 594 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
601 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), 595 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
602 "ror{w}\t{$src2, $dst|$dst, $src2}", 596 "ror{w}\t{$src2, $dst|$dst, $src2}",
603 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))], 597 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
604 IIC_SR>, 598 IIC_SR>, OpSize16;
605 OpSize;
606 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), 599 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
607 "ror{l}\t{$src2, $dst|$dst, $src2}", 600 "ror{l}\t{$src2, $dst|$dst, $src2}",
608 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))], 601 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
609 IIC_SR>; 602 IIC_SR>, OpSize32;
610 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), 603 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
611 (ins GR64:$src1, i8imm:$src2), 604 (ins GR64:$src1, i8imm:$src2),
612 "ror{q}\t{$src2, $dst|$dst, $src2}", 605 "ror{q}\t{$src2, $dst|$dst, $src2}",
613 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))], 606 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
614 IIC_SR>; 607 IIC_SR>;
619 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))], 612 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
620 IIC_SR>; 613 IIC_SR>;
621 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), 614 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
622 "ror{w}\t$dst", 615 "ror{w}\t$dst",
623 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))], 616 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
624 IIC_SR>, OpSize; 617 IIC_SR>, OpSize16;
625 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), 618 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
626 "ror{l}\t$dst", 619 "ror{l}\t$dst",
627 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))], 620 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
628 IIC_SR>; 621 IIC_SR>, OpSize32;
629 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), 622 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
630 "ror{q}\t$dst", 623 "ror{q}\t$dst",
631 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))], 624 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
632 IIC_SR>; 625 IIC_SR>;
633 } // Constraints = "$src = $dst", SchedRW 626 } // Constraints = "$src = $dst", SchedRW
639 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)], 632 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
640 IIC_SR>; 633 IIC_SR>;
641 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), 634 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
642 "ror{w}\t{%cl, $dst|$dst, cl}", 635 "ror{w}\t{%cl, $dst|$dst, cl}",
643 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)], 636 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
644 IIC_SR>, OpSize; 637 IIC_SR>, OpSize16;
645 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), 638 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
646 "ror{l}\t{%cl, $dst|$dst, cl}", 639 "ror{l}\t{%cl, $dst|$dst, cl}",
647 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)], 640 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
648 IIC_SR>; 641 IIC_SR>, OpSize32;
649 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), 642 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
650 "ror{q}\t{%cl, $dst|$dst, cl}", 643 "ror{q}\t{%cl, $dst|$dst, cl}",
651 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)], 644 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
652 IIC_SR>; 645 IIC_SR>;
653 } 646 }
656 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], 649 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
657 IIC_SR>; 650 IIC_SR>;
658 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), 651 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
659 "ror{w}\t{$src, $dst|$dst, $src}", 652 "ror{w}\t{$src, $dst|$dst, $src}",
660 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], 653 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
661 IIC_SR>, 654 IIC_SR>, OpSize16;
662 OpSize;
663 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), 655 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
664 "ror{l}\t{$src, $dst|$dst, $src}", 656 "ror{l}\t{$src, $dst|$dst, $src}",
665 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], 657 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
666 IIC_SR>; 658 IIC_SR>, OpSize32;
667 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src), 659 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
668 "ror{q}\t{$src, $dst|$dst, $src}", 660 "ror{q}\t{$src, $dst|$dst, $src}",
669 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], 661 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
670 IIC_SR>; 662 IIC_SR>;
671 663
675 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)], 667 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
676 IIC_SR>; 668 IIC_SR>;
677 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), 669 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
678 "ror{w}\t$dst", 670 "ror{w}\t$dst",
679 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)], 671 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
680 IIC_SR>, 672 IIC_SR>, OpSize16;
681 OpSize;
682 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), 673 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
683 "ror{l}\t$dst", 674 "ror{l}\t$dst",
684 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)], 675 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
685 IIC_SR>; 676 IIC_SR>, OpSize32;
686 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), 677 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
687 "ror{q}\t$dst", 678 "ror{q}\t$dst",
688 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)], 679 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
689 IIC_SR>; 680 IIC_SR>;
690 } // SchedRW 681 } // SchedRW
700 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), 691 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
701 (ins GR16:$src1, GR16:$src2), 692 (ins GR16:$src1, GR16:$src2),
702 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", 693 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
703 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))], 694 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
704 IIC_SHD16_REG_CL>, 695 IIC_SHD16_REG_CL>,
705 TB, OpSize; 696 TB, OpSize16;
706 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), 697 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
707 (ins GR16:$src1, GR16:$src2), 698 (ins GR16:$src1, GR16:$src2),
708 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", 699 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
709 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))], 700 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
710 IIC_SHD16_REG_CL>, 701 IIC_SHD16_REG_CL>,
711 TB, OpSize; 702 TB, OpSize16;
712 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), 703 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
713 (ins GR32:$src1, GR32:$src2), 704 (ins GR32:$src1, GR32:$src2),
714 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", 705 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
715 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))], 706 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
716 IIC_SHD32_REG_CL>, TB; 707 IIC_SHD32_REG_CL>, TB, OpSize32;
717 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), 708 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
718 (ins GR32:$src1, GR32:$src2), 709 (ins GR32:$src1, GR32:$src2),
719 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", 710 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
720 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))], 711 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
721 IIC_SHD32_REG_CL>, TB; 712 IIC_SHD32_REG_CL>, TB, OpSize32;
722 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), 713 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
723 (ins GR64:$src1, GR64:$src2), 714 (ins GR64:$src1, GR64:$src2),
724 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", 715 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
725 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))], 716 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
726 IIC_SHD64_REG_CL>, 717 IIC_SHD64_REG_CL>,
738 (outs GR16:$dst), 729 (outs GR16:$dst),
739 (ins GR16:$src1, GR16:$src2, i8imm:$src3), 730 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
740 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 731 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
741 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, 732 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
742 (i8 imm:$src3)))], IIC_SHD16_REG_IM>, 733 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
743 TB, OpSize; 734 TB, OpSize16;
744 def SHRD16rri8 : Ii8<0xAC, MRMDestReg, 735 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
745 (outs GR16:$dst), 736 (outs GR16:$dst),
746 (ins GR16:$src1, GR16:$src2, i8imm:$src3), 737 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
747 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 738 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
748 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, 739 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
749 (i8 imm:$src3)))], IIC_SHD16_REG_IM>, 740 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
750 TB, OpSize; 741 TB, OpSize16;
751 def SHLD32rri8 : Ii8<0xA4, MRMDestReg, 742 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
752 (outs GR32:$dst), 743 (outs GR32:$dst),
753 (ins GR32:$src1, GR32:$src2, i8imm:$src3), 744 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
754 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 745 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
755 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, 746 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
756 (i8 imm:$src3)))], IIC_SHD32_REG_IM>, 747 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
757 TB; 748 TB, OpSize32;
758 def SHRD32rri8 : Ii8<0xAC, MRMDestReg, 749 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
759 (outs GR32:$dst), 750 (outs GR32:$dst),
760 (ins GR32:$src1, GR32:$src2, i8imm:$src3), 751 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
761 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 752 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
762 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, 753 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
763 (i8 imm:$src3)))], IIC_SHD32_REG_IM>, 754 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
764 TB; 755 TB, OpSize32;
765 def SHLD64rri8 : RIi8<0xA4, MRMDestReg, 756 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
766 (outs GR64:$dst), 757 (outs GR64:$dst),
767 (ins GR64:$src1, GR64:$src2, i8imm:$src3), 758 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
768 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 759 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
769 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, 760 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
782 let SchedRW = [WriteShiftLd, WriteRMW] in { 773 let SchedRW = [WriteShiftLd, WriteRMW] in {
783 let Uses = [CL] in { 774 let Uses = [CL] in {
784 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 775 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
785 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", 776 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
786 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), 777 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
787 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize; 778 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
788 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 779 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
789 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", 780 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
790 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), 781 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
791 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize; 782 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
792 783
793 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 784 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
794 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", 785 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
795 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), 786 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
796 addr:$dst)], IIC_SHD32_MEM_CL>, TB; 787 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
797 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 788 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
798 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", 789 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
799 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), 790 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
800 addr:$dst)], IIC_SHD32_MEM_CL>, TB; 791 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
801 792
802 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 793 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
803 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", 794 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
804 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL), 795 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
805 addr:$dst)], IIC_SHD64_MEM_CL>, TB; 796 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
813 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), 804 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
814 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 805 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
815 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, 806 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
816 (i8 imm:$src3)), addr:$dst)], 807 (i8 imm:$src3)), addr:$dst)],
817 IIC_SHD16_MEM_IM>, 808 IIC_SHD16_MEM_IM>,
818 TB, OpSize; 809 TB, OpSize16;
819 def SHRD16mri8 : Ii8<0xAC, MRMDestMem, 810 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
820 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), 811 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
821 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 812 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
822 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, 813 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
823 (i8 imm:$src3)), addr:$dst)], 814 (i8 imm:$src3)), addr:$dst)],
824 IIC_SHD16_MEM_IM>, 815 IIC_SHD16_MEM_IM>,
825 TB, OpSize; 816 TB, OpSize16;
826 817
827 def SHLD32mri8 : Ii8<0xA4, MRMDestMem, 818 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
828 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), 819 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
829 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 820 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
830 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, 821 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
831 (i8 imm:$src3)), addr:$dst)], 822 (i8 imm:$src3)), addr:$dst)],
832 IIC_SHD32_MEM_IM>, 823 IIC_SHD32_MEM_IM>,
833 TB; 824 TB, OpSize32;
834 def SHRD32mri8 : Ii8<0xAC, MRMDestMem, 825 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
835 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), 826 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
836 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 827 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
837 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, 828 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
838 (i8 imm:$src3)), addr:$dst)], 829 (i8 imm:$src3)), addr:$dst)],
839 IIC_SHD32_MEM_IM>, 830 IIC_SHD32_MEM_IM>,
840 TB; 831 TB, OpSize32;
841 832
842 def SHLD64mri8 : RIi8<0xA4, MRMDestMem, 833 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
843 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), 834 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
844 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", 835 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
845 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, 836 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
903 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; 894 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W;
904 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; 895 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
905 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; 896 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
906 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; 897 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
907 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W; 898 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
908 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize; 899 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD;
909 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W; 900 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W;
910 901
911 // Prefer RORX which is non-destructive and doesn't update EFLAGS. 902 // Prefer RORX which is non-destructive and doesn't update EFLAGS.
912 let AddedComplexity = 10 in { 903 let AddedComplexity = 10 in {
913 def : Pat<(rotl GR32:$src, (i8 imm:$shamt)), 904 def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
914 (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>; 905 (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;