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comparison test/CodeGen/AArch64/arm64-subvector-extend.ll @ 77:54457678186b

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents
children 1172e4bd9c6f
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equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
2
3 ; Test efficient codegen of vector extends up from legal type to 128 bit
4 ; and 256 bit vector types.
5
6 ;-----
7 ; Vectors of i16.
8 ;-----
9 define <8 x i16> @func1(<8 x i8> %v0) nounwind {
10 ; CHECK-LABEL: func1:
11 ; CHECK-NEXT: ushll.8h v0, v0, #0
12 ; CHECK-NEXT: ret
13 %r = zext <8 x i8> %v0 to <8 x i16>
14 ret <8 x i16> %r
15 }
16
17 define <8 x i16> @func2(<8 x i8> %v0) nounwind {
18 ; CHECK-LABEL: func2:
19 ; CHECK-NEXT: sshll.8h v0, v0, #0
20 ; CHECK-NEXT: ret
21 %r = sext <8 x i8> %v0 to <8 x i16>
22 ret <8 x i16> %r
23 }
24
25 define <16 x i16> @func3(<16 x i8> %v0) nounwind {
26 ; CHECK-LABEL: func3:
27 ; CHECK-NEXT: ushll2.8h v1, v0, #0
28 ; CHECK-NEXT: ushll.8h v0, v0, #0
29 ; CHECK-NEXT: ret
30 %r = zext <16 x i8> %v0 to <16 x i16>
31 ret <16 x i16> %r
32 }
33
34 define <16 x i16> @func4(<16 x i8> %v0) nounwind {
35 ; CHECK-LABEL: func4:
36 ; CHECK-NEXT: sshll2.8h v1, v0, #0
37 ; CHECK-NEXT: sshll.8h v0, v0, #0
38 ; CHECK-NEXT: ret
39 %r = sext <16 x i8> %v0 to <16 x i16>
40 ret <16 x i16> %r
41 }
42
43 ;-----
44 ; Vectors of i32.
45 ;-----
46
47 define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
48 ; CHECK-LABEL: afunc1:
49 ; CHECK-NEXT: ushll.4s v0, v0, #0
50 ; CHECK-NEXT: ret
51 %r = zext <4 x i16> %v0 to <4 x i32>
52 ret <4 x i32> %r
53 }
54
55 define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
56 ; CHECK-LABEL: afunc2:
57 ; CHECK-NEXT: sshll.4s v0, v0, #0
58 ; CHECK-NEXT: ret
59 %r = sext <4 x i16> %v0 to <4 x i32>
60 ret <4 x i32> %r
61 }
62
63 define <8 x i32> @afunc3(<8 x i16> %v0) nounwind {
64 ; CHECK-LABEL: afunc3:
65 ; CHECK-NEXT: ushll2.4s v1, v0, #0
66 ; CHECK-NEXT: ushll.4s v0, v0, #0
67 ; CHECK-NEXT: ret
68 %r = zext <8 x i16> %v0 to <8 x i32>
69 ret <8 x i32> %r
70 }
71
72 define <8 x i32> @afunc4(<8 x i16> %v0) nounwind {
73 ; CHECK-LABEL: afunc4:
74 ; CHECK-NEXT: sshll2.4s v1, v0, #0
75 ; CHECK-NEXT: sshll.4s v0, v0, #0
76 ; CHECK-NEXT: ret
77 %r = sext <8 x i16> %v0 to <8 x i32>
78 ret <8 x i32> %r
79 }
80
81 define <8 x i32> @bfunc1(<8 x i8> %v0) nounwind {
82 ; CHECK-LABEL: bfunc1:
83 ; CHECK-NEXT: ushll.8h v0, v0, #0
84 ; CHECK-NEXT: ushll2.4s v1, v0, #0
85 ; CHECK-NEXT: ushll.4s v0, v0, #0
86 ; CHECK-NEXT: ret
87 %r = zext <8 x i8> %v0 to <8 x i32>
88 ret <8 x i32> %r
89 }
90
91 define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind {
92 ; CHECK-LABEL: bfunc2:
93 ; CHECK-NEXT: sshll.8h v0, v0, #0
94 ; CHECK-NEXT: sshll2.4s v1, v0, #0
95 ; CHECK-NEXT: sshll.4s v0, v0, #0
96 ; CHECK-NEXT: ret
97 %r = sext <8 x i8> %v0 to <8 x i32>
98 ret <8 x i32> %r
99 }
100
101 ;-----
102 ; Vectors of i64.
103 ;-----
104
105 define <4 x i64> @zfunc1(<4 x i32> %v0) nounwind {
106 ; CHECK-LABEL: zfunc1:
107 ; CHECK-NEXT: ushll2.2d v1, v0, #0
108 ; CHECK-NEXT: ushll.2d v0, v0, #0
109 ; CHECK-NEXT: ret
110 %r = zext <4 x i32> %v0 to <4 x i64>
111 ret <4 x i64> %r
112 }
113
114 define <4 x i64> @zfunc2(<4 x i32> %v0) nounwind {
115 ; CHECK-LABEL: zfunc2:
116 ; CHECK-NEXT: sshll2.2d v1, v0, #0
117 ; CHECK-NEXT: sshll.2d v0, v0, #0
118 ; CHECK-NEXT: ret
119 %r = sext <4 x i32> %v0 to <4 x i64>
120 ret <4 x i64> %r
121 }
122
123 define <4 x i64> @bfunc3(<4 x i16> %v0) nounwind {
124 ; CHECK-LABEL: func3:
125 ; CHECK-NEXT: ushll.4s v0, v0, #0
126 ; CHECK-NEXT: ushll2.2d v1, v0, #0
127 ; CHECK-NEXT: ushll.2d v0, v0, #0
128 ; CHECK-NEXT: ret
129 %r = zext <4 x i16> %v0 to <4 x i64>
130 ret <4 x i64> %r
131 }
132
133 define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind {
134 ; CHECK-LABEL: func4:
135 ; CHECK-NEXT: sshll.4s v0, v0, #0
136 ; CHECK-NEXT: sshll2.2d v1, v0, #0
137 ; CHECK-NEXT: sshll.2d v0, v0, #0
138 ; CHECK-NEXT: ret
139 %r = sext <4 x i16> %v0 to <4 x i64>
140 ret <4 x i64> %r
141 }