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comparison test/CodeGen/R600/mad_uint24.ll @ 77:54457678186b

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK 2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
3 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK 3 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
4 4
5 ; EG-CHECK-LABEL: @u32_mad24 5 ; FUNC-LABEL: @u32_mad24
6 ; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X 6 ; EG: MULADD_UINT24
7 ; SI-CHECK-LABEL: @u32_mad24 7 ; SI: V_MAD_U32_U24
8 ; SI-CHECK: V_MAD_U32_U24
9 8
10 define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 9 define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
11 entry: 10 entry:
12 %0 = shl i32 %a, 8 11 %0 = shl i32 %a, 8
13 %a_24 = lshr i32 %0, 8 12 %a_24 = lshr i32 %0, 8
17 %3 = add i32 %2, %c 16 %3 = add i32 %2, %c
18 store i32 %3, i32 addrspace(1)* %out 17 store i32 %3, i32 addrspace(1)* %out
19 ret void 18 ret void
20 } 19 }
21 20
22 ; EG-CHECK-LABEL: @i16_mad24 21 ; FUNC-LABEL: @i16_mad24
23 ; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
24 ; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
25 ; EG-CHECK-DAG: VTX_READ_16 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48
26 ; The order of A and B does not matter. 22 ; The order of A and B does not matter.
27 ; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]] 23 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
28 ; The result must be sign-extended 24 ; The result must be sign-extended
29 ; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x 25 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
30 ; EG-CHECK: 16 26 ; EG: 16
31 ; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x 27 ; SI: V_MAD_U32_U24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
32 ; EG-CHECK: 16 28 ; SI: V_BFE_I32 v{{[0-9]}}, [[MAD]], 0, 16
33 ; SI-CHECK-LABEL: @i16_mad24
34 ; SI-CHECK: V_MAD_U32_U24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
35 ; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 16, [[MAD]]
36 ; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 16, [[LSHL]]
37 29
38 define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) { 30 define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
39 entry: 31 entry:
40 %0 = mul i16 %a, %b 32 %0 = mul i16 %a, %b
41 %1 = add i16 %0, %c 33 %1 = add i16 %0, %c
42 %2 = sext i16 %1 to i32 34 %2 = sext i16 %1 to i32
43 store i32 %2, i32 addrspace(1)* %out 35 store i32 %2, i32 addrspace(1)* %out
44 ret void 36 ret void
45 } 37 }
46 38
47 ; EG-CHECK-LABEL: @i8_mad24 39 ; FUNC-LABEL: @i8_mad24
48 ; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 40 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
49 ; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
50 ; EG-CHECK-DAG: VTX_READ_8 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48
51 ; The order of A and B does not matter.
52 ; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
53 ; The result must be sign-extended 41 ; The result must be sign-extended
54 ; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x 42 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
55 ; EG-CHECK: 24 43 ; EG: 8
56 ; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x 44 ; SI: V_MAD_U32_U24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
57 ; EG-CHECK: 24 45 ; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8
58 ; SI-CHECK-LABEL: @i8_mad24
59 ; SI-CHECK: V_MAD_U32_U24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
60 ; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 24, [[MUL]]
61 ; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 24, [[LSHL]]
62 46
63 define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) { 47 define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
64 entry: 48 entry:
65 %0 = mul i8 %a, %b 49 %0 = mul i8 %a, %b
66 %1 = add i8 %0, %c 50 %1 = add i8 %0, %c
67 %2 = sext i8 %1 to i32 51 %2 = sext i8 %1 to i32
68 store i32 %2, i32 addrspace(1)* %out 52 store i32 %2, i32 addrspace(1)* %out
69 ret void 53 ret void
70 } 54 }
55
56 ; This tests for a bug where the mad_u24 pattern matcher would call
57 ; SimplifyDemandedBits on the first operand of the mul instruction
58 ; assuming that the pattern would be matched to a 24-bit mad. This
59 ; led to some instructions being incorrectly erased when the entire
60 ; 24-bit mad pattern wasn't being matched.
61
62 ; Check that the select instruction is not deleted.
63 ; FUNC-LABEL: @i24_i32_i32_mad
64 ; EG: CNDE_INT
65 ; SI: V_CNDMASK
66 define void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
67 entry:
68 %0 = ashr i32 %a, 8
69 %1 = icmp ne i32 %c, 0
70 %2 = select i1 %1, i32 %0, i32 34
71 %3 = mul i32 %2, %c
72 %4 = add i32 %3, %d
73 store i32 %4, i32 addrspace(1)* %out
74 ret void
75 }