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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
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children 803732b1fca8
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78:af83660cff7b 83:60c9769439b8
1 //=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the machine model for AMD btver2 (Jaguar) to support
11 // instruction scheduling and other instruction cost heuristics. Based off AMD Software
12 // Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
13 //
14 //===----------------------------------------------------------------------===//
15
16 def BtVer2Model : SchedMachineModel {
17 // All x86 instructions are modeled as a single micro-op, and btver2 can
18 // decode 2 instructions per cycle.
19 let IssueWidth = 2;
20 let MicroOpBufferSize = 64; // Retire Control Unit
21 let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
22 let HighLatency = 25;
23 let MispredictPenalty = 14; // Minimum branch misdirection penalty
24 let PostRAScheduler = 1;
25
26 // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
28 let CompleteModel = 0;
29 }
30
31 let SchedModel = BtVer2Model in {
32
33 // Jaguar can issue up to 6 micro-ops in one cycle
34 def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
35 def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
36 def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
37 def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
38 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
39 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
40
41 // Any pipe - FIXME we need this until we can discriminate between int/fpu load/store/moves properly
42 def JAny : ProcResGroup<[JALU0, JALU1, JLAGU, JSAGU, JFPU0, JFPU1]>;
43
44 // Integer Pipe Scheduler
45 def JALU01 : ProcResGroup<[JALU0, JALU1]> {
46 let BufferSize=20;
47 }
48
49 // AGU Pipe Scheduler
50 def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> {
51 let BufferSize=12;
52 }
53
54 // Fpu Pipe Scheduler
55 def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> {
56 let BufferSize=18;
57 }
58
59 def JDiv : ProcResource<1>; // integer division
60 def JMul : ProcResource<1>; // integer multiplication
61 def JVALU0 : ProcResource<1>; // vector integer
62 def JVALU1 : ProcResource<1>; // vector integer
63 def JVIMUL : ProcResource<1>; // vector integer multiplication
64 def JSTC : ProcResource<1>; // vector store/convert
65 def JFPM : ProcResource<1>; // FP multiplication
66 def JFPA : ProcResource<1>; // FP addition
67
68 // Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
69 // cycles after the memory operand.
70 def : ReadAdvance<ReadAfterLd, 3>;
71
72 // Many SchedWrites are defined in pairs with and without a folded load.
73 // Instructions with folded loads are usually micro-fused, so they only appear
74 // as two micro-ops when dispatched by the schedulers.
75 // This multiclass defines the resource usage for variants with and without
76 // folded loads.
77 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
78 ProcResourceKind ExePort,
79 int Lat> {
80 // Register variant is using a single cycle on ExePort.
81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
82
83 // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
84 // latency.
85 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
86 let Latency = !add(Lat, 3);
87 }
88 }
89
90 multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
91 ProcResourceKind ExePort,
92 int Lat> {
93 // Register variant is using a single cycle on ExePort.
94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
95
96 // Memory variant also uses a cycle on JLAGU and adds 5 cycles to the
97 // latency.
98 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
99 let Latency = !add(Lat, 5);
100 }
101 }
102
103 // A folded store needs a cycle on the SAGU for the store data.
104 def : WriteRes<WriteRMW, [JSAGU]>;
105
106 ////////////////////////////////////////////////////////////////////////////////
107 // Arithmetic.
108 ////////////////////////////////////////////////////////////////////////////////
109
110 defm : JWriteResIntPair<WriteALU, JALU01, 1>;
111 defm : JWriteResIntPair<WriteIMul, JALU1, 3>;
112
113 def : WriteRes<WriteIMulH, [JALU1]> {
114 let Latency = 6;
115 let ResourceCycles = [4];
116 }
117
118 // FIXME 8/16 bit divisions
119 def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
120 let Latency = 25;
121 let ResourceCycles = [1, 25];
122 }
123 def : WriteRes<WriteIDivLd, [JALU1, JLAGU, JDiv]> {
124 let Latency = 41;
125 let ResourceCycles = [1, 1, 25];
126 }
127
128 // This is for simple LEAs with one or two input operands.
129 // FIXME: SAGU 3-operand LEA
130 def : WriteRes<WriteLEA, [JALU01]>;
131
132 ////////////////////////////////////////////////////////////////////////////////
133 // Integer shifts and rotates.
134 ////////////////////////////////////////////////////////////////////////////////
135
136 defm : JWriteResIntPair<WriteShift, JALU01, 1>;
137
138 ////////////////////////////////////////////////////////////////////////////////
139 // Loads, stores, and moves, not folded with other operations.
140 // FIXME: Split x86 and SSE load/store/moves
141 ////////////////////////////////////////////////////////////////////////////////
142
143 def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
144 def : WriteRes<WriteStore, [JSAGU]>;
145 def : WriteRes<WriteMove, [JAny]>;
146
147 ////////////////////////////////////////////////////////////////////////////////
148 // Idioms that clear a register, like xorps %xmm0, %xmm0.
149 // These can often bypass execution ports completely.
150 ////////////////////////////////////////////////////////////////////////////////
151
152 def : WriteRes<WriteZero, []>;
153
154 ////////////////////////////////////////////////////////////////////////////////
155 // Branches don't produce values, so they have no latency, but they still
156 // consume resources. Indirect branches can fold loads.
157 ////////////////////////////////////////////////////////////////////////////////
158
159 defm : JWriteResIntPair<WriteJump, JALU01, 1>;
160
161 ////////////////////////////////////////////////////////////////////////////////
162 // Floating point. This covers both scalar and vector operations.
163 // FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions?
164 // FIXME: Double precision latencies
165 // FIXME: SS vs PS latencies
166 // FIXME: ymm latencies
167 ////////////////////////////////////////////////////////////////////////////////
168
169 defm : JWriteResFpuPair<WriteFAdd, JFPU0, 3>;
170 defm : JWriteResFpuPair<WriteFMul, JFPU1, 2>;
171 defm : JWriteResFpuPair<WriteFRcp, JFPU1, 2>;
172 defm : JWriteResFpuPair<WriteFRsqrt, JFPU1, 2>;
173 defm : JWriteResFpuPair<WriteFShuffle, JFPU01, 1>;
174 defm : JWriteResFpuPair<WriteFBlend, JFPU01, 1>;
175 defm : JWriteResFpuPair<WriteFShuffle256, JFPU01, 1>;
176
177 def : WriteRes<WriteFSqrt, [JFPU1, JLAGU, JFPM]> {
178 let Latency = 21;
179 let ResourceCycles = [1, 1, 21];
180 }
181 def : WriteRes<WriteFSqrtLd, [JFPU1, JLAGU, JFPM]> {
182 let Latency = 26;
183 let ResourceCycles = [1, 1, 21];
184 }
185
186 def : WriteRes<WriteFDiv, [JFPU1, JLAGU, JFPM]> {
187 let Latency = 19;
188 let ResourceCycles = [1, 1, 19];
189 }
190 def : WriteRes<WriteFDivLd, [JFPU1, JLAGU, JFPM]> {
191 let Latency = 24;
192 let ResourceCycles = [1, 1, 19];
193 }
194
195 // FIXME: integer pipes
196 defm : JWriteResFpuPair<WriteCvtF2I, JFPU1, 3>; // Float -> Integer.
197 defm : JWriteResFpuPair<WriteCvtI2F, JFPU1, 3>; // Integer -> Float.
198 defm : JWriteResFpuPair<WriteCvtF2F, JFPU1, 3>; // Float -> Float size conversion.
199
200 def : WriteRes<WriteFVarBlend, [JFPU01]> {
201 let Latency = 2;
202 let ResourceCycles = [2];
203 }
204 def : WriteRes<WriteFVarBlendLd, [JLAGU, JFPU01]> {
205 let Latency = 7;
206 let ResourceCycles = [1, 2];
207 }
208
209 // Vector integer operations.
210 defm : JWriteResFpuPair<WriteVecALU, JFPU01, 1>;
211 defm : JWriteResFpuPair<WriteVecShift, JFPU01, 1>;
212 defm : JWriteResFpuPair<WriteVecIMul, JFPU0, 2>;
213 defm : JWriteResFpuPair<WriteShuffle, JFPU01, 1>;
214 defm : JWriteResFpuPair<WriteBlend, JFPU01, 1>;
215 defm : JWriteResFpuPair<WriteVecLogic, JFPU01, 1>;
216 defm : JWriteResFpuPair<WriteShuffle256, JFPU01, 1>;
217
218 def : WriteRes<WriteVarBlend, [JFPU01]> {
219 let Latency = 2;
220 let ResourceCycles = [2];
221 }
222 def : WriteRes<WriteVarBlendLd, [JLAGU, JFPU01]> {
223 let Latency = 7;
224 let ResourceCycles = [1, 2];
225 }
226
227 // FIXME: why do we need to define AVX2 resource on CPU that doesn't have AVX2?
228 def : WriteRes<WriteVarVecShift, [JFPU01]> {
229 let Latency = 1;
230 let ResourceCycles = [1];
231 }
232 def : WriteRes<WriteVarVecShiftLd, [JLAGU, JFPU01]> {
233 let Latency = 6;
234 let ResourceCycles = [1, 1];
235 }
236
237 def : WriteRes<WriteMPSAD, [JFPU0]> {
238 let Latency = 3;
239 let ResourceCycles = [2];
240 }
241 def : WriteRes<WriteMPSADLd, [JLAGU, JFPU0]> {
242 let Latency = 8;
243 let ResourceCycles = [1, 2];
244 }
245
246 ////////////////////////////////////////////////////////////////////////////////
247 // String instructions.
248 // Packed Compare Implicit Length Strings, Return Mask
249 // FIXME: approximate latencies + pipe dependencies
250 ////////////////////////////////////////////////////////////////////////////////
251
252 def : WriteRes<WritePCmpIStrM, [JFPU01]> {
253 let Latency = 7;
254 let ResourceCycles = [2];
255 }
256 def : WriteRes<WritePCmpIStrMLd, [JLAGU, JFPU01]> {
257 let Latency = 12;
258 let ResourceCycles = [1, 2];
259 }
260
261 // Packed Compare Explicit Length Strings, Return Mask
262 def : WriteRes<WritePCmpEStrM, [JFPU01]> {
263 let Latency = 13;
264 let ResourceCycles = [5];
265 }
266 def : WriteRes<WritePCmpEStrMLd, [JLAGU, JFPU01]> {
267 let Latency = 18;
268 let ResourceCycles = [1, 5];
269 }
270
271 // Packed Compare Implicit Length Strings, Return Index
272 def : WriteRes<WritePCmpIStrI, [JFPU01]> {
273 let Latency = 6;
274 let ResourceCycles = [2];
275 }
276 def : WriteRes<WritePCmpIStrILd, [JLAGU, JFPU01]> {
277 let Latency = 11;
278 let ResourceCycles = [1, 2];
279 }
280
281 // Packed Compare Explicit Length Strings, Return Index
282 def : WriteRes<WritePCmpEStrI, [JFPU01]> {
283 let Latency = 13;
284 let ResourceCycles = [5];
285 }
286 def : WriteRes<WritePCmpEStrILd, [JLAGU, JFPU01]> {
287 let Latency = 18;
288 let ResourceCycles = [1, 5];
289 }
290
291 ////////////////////////////////////////////////////////////////////////////////
292 // AES Instructions.
293 ////////////////////////////////////////////////////////////////////////////////
294
295 def : WriteRes<WriteAESDecEnc, [JFPU01, JVIMUL]> {
296 let Latency = 3;
297 let ResourceCycles = [1, 1];
298 }
299 def : WriteRes<WriteAESDecEncLd, [JFPU01, JLAGU, JVIMUL]> {
300 let Latency = 8;
301 let ResourceCycles = [1, 1, 1];
302 }
303
304 def : WriteRes<WriteAESIMC, [JVIMUL]> {
305 let Latency = 2;
306 let ResourceCycles = [1];
307 }
308 def : WriteRes<WriteAESIMCLd, [JLAGU, JVIMUL]> {
309 let Latency = 7;
310 let ResourceCycles = [1, 1];
311 }
312
313 def : WriteRes<WriteAESKeyGen, [JVIMUL]> {
314 let Latency = 2;
315 let ResourceCycles = [1];
316 }
317 def : WriteRes<WriteAESKeyGenLd, [JLAGU, JVIMUL]> {
318 let Latency = 7;
319 let ResourceCycles = [1, 1];
320 }
321
322 ////////////////////////////////////////////////////////////////////////////////
323 // Carry-less multiplication instructions.
324 ////////////////////////////////////////////////////////////////////////////////
325
326 def : WriteRes<WriteCLMul, [JVIMUL]> {
327 let Latency = 2;
328 let ResourceCycles = [1];
329 }
330 def : WriteRes<WriteCLMulLd, [JLAGU, JVIMUL]> {
331 let Latency = 7;
332 let ResourceCycles = [1, 1];
333 }
334
335 // FIXME: pipe for system/microcode?
336 def : WriteRes<WriteSystem, [JAny]> { let Latency = 100; }
337 def : WriteRes<WriteMicrocoded, [JAny]> { let Latency = 100; }
338 def : WriteRes<WriteFence, [JSAGU]>;
339 def : WriteRes<WriteNop, []>;
340 } // SchedModel
341