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comparison test/CodeGen/AArch64/aarch64-wide-shuffle.ll @ 83:60c9769439b8

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
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78:af83660cff7b 83:60c9769439b8
1 ; RUN: llc < %s | FileCheck %s
2
3 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
4 target triple = "aarch64-unknown-linux-gnu"
5
6 define <4 x i16> @f(<4 x i32> %vqdmlal_v3.i, <8 x i16> %x5) {
7 entry:
8 ; Check that we don't just dup the input vector. The code emitted is ext, dup, ext, ext
9 ; but only match the last three instructions as the first two could be combined to
10 ; a dup2 at some stage.
11 ; CHECK: dup
12 ; CHECK: ext
13 ; CHECK: ext
14 %x4 = extractelement <4 x i32> %vqdmlal_v3.i, i32 2
15 %vgetq_lane = trunc i32 %x4 to i16
16 %vecinit.i = insertelement <4 x i16> undef, i16 %vgetq_lane, i32 0
17 %vecinit2.i = insertelement <4 x i16> %vecinit.i, i16 %vgetq_lane, i32 2
18 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vgetq_lane, i32 3
19 %vgetq_lane261 = extractelement <8 x i16> %x5, i32 0
20 %vset_lane267 = insertelement <4 x i16> %vecinit3.i, i16 %vgetq_lane261, i32 1
21 ret <4 x i16> %vset_lane267
22 }