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comparison test/CodeGen/AArch64/neon-scalar-copy.ll @ 83:60c9769439b8

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children 803732b1fca8
comparison
equal deleted inserted replaced
78:af83660cff7b 83:60c9769439b8
1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefix=CHECK 1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s
2 2
3 3 define float @test_dup_sv2S(<2 x float> %v) #0 {
4 define float @test_dup_sv2S(<2 x float> %v) { 4 ; CHECK-LABEL: test_dup_sv2S:
5 ; CHECK-LABEL: test_dup_sv2S 5 ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
6 ; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] 6 ; CHECK-NEXT: ret
7 %tmp1 = extractelement <2 x float> %v, i32 1 7 %tmp1 = extractelement <2 x float> %v, i32 1
8 ret float %tmp1 8 ret float %tmp1
9 } 9 }
10 10
11 define float @test_dup_sv2S_0(<2 x float> %v) { 11 define float @test_dup_sv2S_0(<2 x float> %v) #0 {
12 ; CHECK-LABEL: test_dup_sv2S_0 12 ; CHECK-LABEL: test_dup_sv2S_0:
13 ; CHECK-NOT: dup {{[vsd][0-9]+}} 13 ; CHECK-NOT: dup {{[vsd][0-9]+}}
14 ; CHECK-NOT: ins {{[vsd][0-9]+}} 14 ; CHECK-NOT: ins {{[vsd][0-9]+}}
15 ; CHECK: ret 15 ; CHECK-NEXT: ret
16 %tmp1 = extractelement <2 x float> %v, i32 0 16 %tmp1 = extractelement <2 x float> %v, i32 0
17 ret float %tmp1 17 ret float %tmp1
18 } 18 }
19 19
20 define float @test_dup_sv4S(<4 x float> %v) { 20 define float @test_dup_sv4S(<4 x float> %v) #0 {
21 ; CHECK-LABEL: test_dup_sv4S 21 ; CHECK-LABEL: test_dup_sv4S:
22 ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
23 ; CHECK-NEXT: ret
24 %tmp1 = extractelement <4 x float> %v, i32 1
25 ret float %tmp1
26 }
27
28 define float @test_dup_sv4S_0(<4 x float> %v) #0 {
29 ; CHECK-LABEL: test_dup_sv4S_0:
22 ; CHECK-NOT: dup {{[vsd][0-9]+}} 30 ; CHECK-NOT: dup {{[vsd][0-9]+}}
23 ; CHECK-NOT: ins {{[vsd][0-9]+}} 31 ; CHECK-NOT: ins {{[vsd][0-9]+}}
24 ; CHECK: ret 32 ; CHECK-NEXT: ret
25 %tmp1 = extractelement <4 x float> %v, i32 0 33 %tmp1 = extractelement <4 x float> %v, i32 0
26 ret float %tmp1 34 ret float %tmp1
27 } 35 }
28 36
29 define double @test_dup_dvD(<1 x double> %v) { 37 define double @test_dup_dvD(<1 x double> %v) #0 {
30 ; CHECK-LABEL: test_dup_dvD 38 ; CHECK-LABEL: test_dup_dvD:
31 ; CHECK-NOT: dup {{[vsd][0-9]+}} 39 ; CHECK-NOT: dup {{[vsd][0-9]+}}
32 ; CHECK-NOT: ins {{[vsd][0-9]+}} 40 ; CHECK-NOT: ins {{[vsd][0-9]+}}
33 ; CHECK: ret 41 ; CHECK-NEXT: ret
34 %tmp1 = extractelement <1 x double> %v, i32 0 42 %tmp1 = extractelement <1 x double> %v, i32 0
35 ret double %tmp1 43 ret double %tmp1
36 } 44 }
37 45
38 define double @test_dup_dv2D(<2 x double> %v) { 46 define double @test_dup_dv2D(<2 x double> %v) #0 {
39 ; CHECK-LABEL: test_dup_dv2D 47 ; CHECK-LABEL: test_dup_dv2D:
40 ; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] 48 ; CHECK-NEXT: mov d{{[0-9]+}}, {{v[0-9]+}}.d[1]
49 ; CHECK-NEXT: ret
41 %tmp1 = extractelement <2 x double> %v, i32 1 50 %tmp1 = extractelement <2 x double> %v, i32 1
42 ret double %tmp1 51 ret double %tmp1
43 } 52 }
44 53
45 define double @test_dup_dv2D_0(<2 x double> %v) { 54 define double @test_dup_dv2D_0(<2 x double> %v) #0 {
46 ; CHECK-LABEL: test_dup_dv2D_0 55 ; CHECK-LABEL: test_dup_dv2D_0:
47 ; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] 56 ; CHECK-NOT: dup {{[vsd][0-9]+}}
48 ; CHECK: ret 57 ; CHECK-NOT: ins {{[vsd][0-9]+}}
49 %tmp1 = extractelement <2 x double> %v, i32 1 58 ; CHECK-NEXT: ret
59 %tmp1 = extractelement <2 x double> %v, i32 0
50 ret double %tmp1 60 ret double %tmp1
51 } 61 }
52 62
53 define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) { 63 define half @test_dup_hv8H(<8 x half> %v) #0 {
54 ; CHECK-LABEL: test_vector_dup_bv16B 64 ; CHECK-LABEL: test_dup_hv8H:
65 ; CHECK-NEXT: mov h{{[0-9]+}}, {{v[0-9]+}}.h[1]
66 ; CHECK-NEXT: ret
67 %tmp1 = extractelement <8 x half> %v, i32 1
68 ret half %tmp1
69 }
70
71 define half @test_dup_hv8H_0(<8 x half> %v) #0 {
72 ; CHECK-LABEL: test_dup_hv8H_0:
73 ; CHECK-NOT: dup {{[vsdh][0-9]+}}
74 ; CHECK-NOT: ins {{[vsdh][0-9]+}}
75 ; CHECK-NEXT: ret
76 %tmp1 = extractelement <8 x half> %v, i32 0
77 ret half %tmp1
78 }
79
80 define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 {
81 ; CHECK-LABEL: test_vector_dup_bv16B:
82 ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.b[14]
83 ; CHECK-NEXT: fmov s0, [[W]]
84 ; CHECK-NEXT: ret
55 %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14> 85 %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14>
56 ret <1 x i8> %shuffle.i 86 ret <1 x i8> %shuffle.i
57 } 87 }
58 88
59 define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) { 89 define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 {
60 ; CHECK-LABEL: test_vector_dup_bv8B 90 ; CHECK-LABEL: test_vector_dup_bv8B:
91 ; CHECK-NEXT: dup v0.8b, v0.b[7]
92 ; CHECK-NEXT: ret
61 %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7> 93 %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7>
62 ret <1 x i8> %shuffle.i 94 ret <1 x i8> %shuffle.i
63 } 95 }
64 96
65 define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) { 97 define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 {
66 ; CHECK-LABEL: test_vector_dup_hv8H 98 ; CHECK-LABEL: test_vector_dup_hv8H:
99 ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.h[7]
100 ; CHECK-NEXT: fmov s0, [[W]]
101 ; CHECK-NEXT: ret
67 %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7> 102 %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7>
68 ret <1 x i16> %shuffle.i 103 ret <1 x i16> %shuffle.i
69 } 104 }
70 105
71 define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) { 106 define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 {
72 ; CHECK-LABEL: test_vector_dup_hv4H 107 ; CHECK-LABEL: test_vector_dup_hv4H:
108 ; CHECK-NEXT: dup v0.4h, v0.h[3]
109 ; CHECK-NEXT: ret
73 %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3> 110 %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3>
74 ret <1 x i16> %shuffle.i 111 ret <1 x i16> %shuffle.i
75 } 112 }
76 113
77 define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) { 114 define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
78 ; CHECK-LABEL: test_vector_dup_sv4S 115 ; CHECK-LABEL: test_vector_dup_sv4S:
116 ; CHECK-NEXT: mov [[W:w[0-9]+]], v0.s[3]
117 ; CHECK-NEXT: fmov s0, [[W]]
118 ; CHECK-NEXT: ret
79 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3> 119 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3>
80 ret <1 x i32> %shuffle 120 ret <1 x i32> %shuffle
81 } 121 }
82 122
83 define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) { 123 define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) #0 {
84 ; CHECK-LABEL: test_vector_dup_sv2S 124 ; CHECK-LABEL: test_vector_dup_sv2S:
125 ; CHECK-NEXT: dup v0.2s, v0.s[1]
126 ; CHECK-NEXT: ret
85 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1> 127 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1>
86 ret <1 x i32> %shuffle 128 ret <1 x i32> %shuffle
87 } 129 }
88 130
89 define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) { 131 define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 {
90 ; CHECK-LABEL: test_vector_dup_dv2D 132 ; CHECK-LABEL: test_vector_dup_dv2D:
91 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8 133 ; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
134 ; CHECK-NEXT: ret
92 %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1> 135 %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1>
93 ret <1 x i64> %shuffle.i 136 ret <1 x i64> %shuffle.i
94 } 137 }
95 138
96 define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) { 139 define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
97 ; CHECK-LABEL: test_vector_copy_dup_dv2D 140 ; CHECK-LABEL: test_vector_copy_dup_dv2D:
98 ; CHECK: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1] 141 ; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
142 ; CHECK-NEXT: ret
99 %vget_lane = extractelement <2 x i64> %c, i32 1 143 %vget_lane = extractelement <2 x i64> %c, i32 1
100 %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0 144 %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
101 ret <1 x i64> %vset_lane 145 ret <1 x i64> %vset_lane
102 } 146 }
103 147
116 ; CHECK-LABEL: test_out_of_range_insert: 160 ; CHECK-LABEL: test_out_of_range_insert:
117 ; CHECK: ret 161 ; CHECK: ret
118 insertelement <4 x i32> %vec, i32 %elt, i32 4 162 insertelement <4 x i32> %vec, i32 %elt, i32 4
119 ret void 163 ret void
120 } 164 }
165
166 attributes #0 = { nounwind }