Mercurial > hg > Members > tobaru > cbc > CbC_llvm
comparison lib/Target/X86/X86InstrXOP.td @ 100:7d135dc70f03
LLVM 3.9
author | Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> |
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date | Tue, 26 Jan 2016 22:53:40 +0900 (2016-01-26) |
parents | afa8332a0e37 |
children | 1172e4bd9c6f |
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96:6418606d0ead | 100:7d135dc70f03 |
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106 (vt128 VR128:$src2))))]>, | 106 (vt128 VR128:$src2))))]>, |
107 XOP_4VOp3, Sched<[WriteVarVecShift, ReadAfterLd]>; | 107 XOP_4VOp3, Sched<[WriteVarVecShift, ReadAfterLd]>; |
108 } | 108 } |
109 | 109 |
110 let ExeDomain = SSEPackedInt in { | 110 let ExeDomain = SSEPackedInt in { |
111 defm VPROTB : xop3op<0x90, "vprotb", X86vprot, v16i8>; | |
112 defm VPROTD : xop3op<0x92, "vprotd", X86vprot, v4i32>; | |
113 defm VPROTQ : xop3op<0x93, "vprotq", X86vprot, v2i64>; | |
114 defm VPROTW : xop3op<0x91, "vprotw", X86vprot, v8i16>; | |
111 defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8>; | 115 defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8>; |
112 defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32>; | 116 defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32>; |
113 defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64>; | 117 defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64>; |
114 defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16>; | 118 defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16>; |
115 defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8>; | 119 defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8>; |
116 defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32>; | 120 defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32>; |
117 defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64>; | 121 defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64>; |
118 defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16>; | 122 defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16>; |
119 } | 123 } |
120 | 124 |
121 multiclass xop3op_int<bits<8> opc, string OpcodeStr, Intrinsic Int> { | 125 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode, |
122 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), | 126 ValueType vt128> { |
123 (ins VR128:$src1, VR128:$src2), | |
124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), | |
125 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, XOP_4VOp3; | |
126 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), | |
127 (ins VR128:$src1, i128mem:$src2), | |
128 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), | |
129 [(set VR128:$dst, | |
130 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2))))]>, | |
131 XOP_4V, VEX_W; | |
132 def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst), | |
133 (ins i128mem:$src1, VR128:$src2), | |
134 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), | |
135 [(set VR128:$dst, | |
136 (Int (bitconvert (loadv2i64 addr:$src1)), VR128:$src2))]>, | |
137 XOP_4VOp3; | |
138 } | |
139 | |
140 let ExeDomain = SSEPackedInt in { | |
141 defm VPROTW : xop3op_int<0x91, "vprotw", int_x86_xop_vprotw>; | |
142 defm VPROTQ : xop3op_int<0x93, "vprotq", int_x86_xop_vprotq>; | |
143 defm VPROTD : xop3op_int<0x92, "vprotd", int_x86_xop_vprotd>; | |
144 defm VPROTB : xop3op_int<0x90, "vprotb", int_x86_xop_vprotb>; | |
145 } | |
146 | |
147 multiclass xop3opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> { | |
148 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), | 127 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), |
149 (ins VR128:$src1, u8imm:$src2), | 128 (ins VR128:$src1, u8imm:$src2), |
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), | 129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
151 [(set VR128:$dst, (Int VR128:$src1, imm:$src2))]>, XOP; | 130 [(set VR128:$dst, |
131 (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP; | |
152 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), | 132 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), |
153 (ins i128mem:$src1, u8imm:$src2), | 133 (ins i128mem:$src1, u8imm:$src2), |
154 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), | 134 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
155 [(set VR128:$dst, | 135 [(set VR128:$dst, |
156 (Int (bitconvert (loadv2i64 addr:$src1)), imm:$src2))]>, XOP; | 136 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP; |
157 } | 137 } |
158 | 138 |
159 let ExeDomain = SSEPackedInt in { | 139 let ExeDomain = SSEPackedInt in { |
160 defm VPROTW : xop3opimm<0xC1, "vprotw", int_x86_xop_vprotwi>; | 140 defm VPROTB : xop3opimm<0xC0, "vprotb", X86vproti, v16i8>; |
161 defm VPROTQ : xop3opimm<0xC3, "vprotq", int_x86_xop_vprotqi>; | 141 defm VPROTD : xop3opimm<0xC2, "vprotd", X86vproti, v4i32>; |
162 defm VPROTD : xop3opimm<0xC2, "vprotd", int_x86_xop_vprotdi>; | 142 defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vproti, v2i64>; |
163 defm VPROTB : xop3opimm<0xC0, "vprotb", int_x86_xop_vprotbi>; | 143 defm VPROTW : xop3opimm<0xC1, "vprotw", X86vproti, v8i16>; |
164 } | 144 } |
165 | 145 |
166 // Instruction where second source can be memory, but third must be register | 146 // Instruction where second source can be memory, but third must be register |
167 multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> { | 147 multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> { |
168 let isCommutable = 1 in | 148 let isCommutable = 1 in |
299 } | 279 } |
300 | 280 |
301 let ExeDomain = SSEPackedInt in | 281 let ExeDomain = SSEPackedInt in |
302 defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>; | 282 defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>; |
303 | 283 |
284 let Predicates = [HasXOP] in { | |
285 def : Pat<(v2i64 (or (and VR128:$src3, VR128:$src1), | |
286 (X86andnp VR128:$src3, VR128:$src2))), | |
287 (VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>; | |
288 | |
289 def : Pat<(v4i64 (or (and VR256:$src3, VR256:$src1), | |
290 (X86andnp VR256:$src3, VR256:$src2))), | |
291 (VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>; | |
292 } | |
293 | |
304 multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128, | 294 multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128, |
305 Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> { | 295 Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> { |
306 def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst), | 296 def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst), |
307 (ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4), | 297 (ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4), |
308 !strconcat(OpcodeStr, | 298 !strconcat(OpcodeStr, |