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comparison test/CodeGen/NVPTX/arithmetic-int.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents 54457678186b
children
comparison
equal deleted inserted replaced
96:6418606d0ead 100:7d135dc70f03
27 ; CHECK: ret 27 ; CHECK: ret
28 %ret = mul i64 %a, %b 28 %ret = mul i64 %a, %b
29 ret i64 %ret 29 ret i64 %ret
30 } 30 }
31 31
32 define i64 @umul_lohi_i64(i64 %a) {
33 ; CHECK-LABEL: umul_lohi_i64(
34 entry:
35 %0 = zext i64 %a to i128
36 %1 = mul i128 %0, 288
37 ; CHECK: mul.lo.{{u|s}}64
38 ; CHECK: mul.hi.{{u|s}}64
39 %2 = lshr i128 %1, 1
40 %3 = trunc i128 %2 to i64
41 ret i64 %3
42 }
43
44 define i64 @smul_lohi_i64(i64 %a) {
45 ; CHECK-LABEL: smul_lohi_i64(
46 entry:
47 %0 = sext i64 %a to i128
48 %1 = mul i128 %0, 288
49 ; CHECK: mul.lo.{{u|s}}64
50 ; CHECK: mul.hi.{{u|s}}64
51 %2 = ashr i128 %1, 1
52 %3 = trunc i128 %2 to i64
53 ret i64 %3
54 }
55
32 define i64 @sdiv_i64(i64 %a, i64 %b) { 56 define i64 @sdiv_i64(i64 %a, i64 %b) {
33 ; CHECK: div.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}} 57 ; CHECK: div.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
34 ; CHECK: ret 58 ; CHECK: ret
35 %ret = sdiv i64 %a, %b 59 %ret = sdiv i64 %a, %b
36 ret i64 %ret 60 ret i64 %ret