Mercurial > hg > Members > tobaru > cbc > CbC_llvm
comparison lib/Target/ARC/ARCISelLowering.h @ 121:803732b1fca8
LLVM 5.0
author | kono |
---|---|
date | Fri, 27 Oct 2017 17:07:41 +0900 |
parents | |
children |
comparison
equal
deleted
inserted
replaced
120:1172e4bd9c6f | 121:803732b1fca8 |
---|---|
1 //===- ARCISelLowering.h - ARC DAG Lowering Interface -----------*- C++ -*-===// | |
2 // | |
3 // The LLVM Compiler Infrastructure | |
4 // | |
5 // This file is distributed under the University of Illinois Open Source | |
6 // License. See LICENSE.TXT for details. | |
7 // | |
8 //===----------------------------------------------------------------------===// | |
9 // | |
10 // This file defines the interfaces that ARC uses to lower LLVM code into a | |
11 // selection DAG. | |
12 // | |
13 //===----------------------------------------------------------------------===// | |
14 | |
15 #ifndef LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H | |
16 #define LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H | |
17 | |
18 #include "ARC.h" | |
19 #include "llvm/CodeGen/SelectionDAG.h" | |
20 #include "llvm/Target/TargetLowering.h" | |
21 | |
22 namespace llvm { | |
23 | |
24 // Forward delcarations | |
25 class ARCSubtarget; | |
26 class ARCTargetMachine; | |
27 | |
28 namespace ARCISD { | |
29 | |
30 enum NodeType : unsigned { | |
31 // Start the numbering where the builtin ops and target ops leave off. | |
32 FIRST_NUMBER = ISD::BUILTIN_OP_END, | |
33 | |
34 // Branch and link (call) | |
35 BL, | |
36 | |
37 // Jump and link (indirect call) | |
38 JL, | |
39 | |
40 // CMP | |
41 CMP, | |
42 | |
43 // CMOV | |
44 CMOV, | |
45 | |
46 // BRcc | |
47 BRcc, | |
48 | |
49 // Global Address Wrapper | |
50 GAWRAPPER, | |
51 | |
52 // return, (j_s [blink]) | |
53 RET | |
54 }; | |
55 | |
56 } // end namespace ARCISD | |
57 | |
58 //===--------------------------------------------------------------------===// | |
59 // TargetLowering Implementation | |
60 //===--------------------------------------------------------------------===// | |
61 class ARCTargetLowering : public TargetLowering { | |
62 public: | |
63 explicit ARCTargetLowering(const TargetMachine &TM, | |
64 const ARCSubtarget &Subtarget); | |
65 | |
66 /// Provide custom lowering hooks for some operations. | |
67 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; | |
68 | |
69 /// This method returns the name of a target specific DAG node. | |
70 const char *getTargetNodeName(unsigned Opcode) const override; | |
71 | |
72 /// Return true if the addressing mode represented by AM is legal for this | |
73 /// target, for a load/store of the specified type. | |
74 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, | |
75 unsigned AS, | |
76 Instruction *I = nullptr) const override; | |
77 | |
78 private: | |
79 const TargetMachine &TM; | |
80 const ARCSubtarget &Subtarget; | |
81 | |
82 // Lower Operand helpers | |
83 SDValue LowerCallArguments(SDValue Chain, CallingConv::ID CallConv, | |
84 bool isVarArg, | |
85 const SmallVectorImpl<ISD::InputArg> &Ins, | |
86 SDLoc dl, SelectionDAG &DAG, | |
87 SmallVectorImpl<SDValue> &InVals) const; | |
88 // Lower Operand specifics | |
89 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; | |
90 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; | |
91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; | |
92 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; | |
93 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; | |
94 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; | |
95 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; | |
96 | |
97 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, | |
98 bool isVarArg, | |
99 const SmallVectorImpl<ISD::InputArg> &Ins, | |
100 const SDLoc &dl, SelectionDAG &DAG, | |
101 SmallVectorImpl<SDValue> &InVals) const override; | |
102 | |
103 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, | |
104 SmallVectorImpl<SDValue> &InVals) const override; | |
105 | |
106 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, | |
107 const SmallVectorImpl<ISD::OutputArg> &Outs, | |
108 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, | |
109 SelectionDAG &DAG) const override; | |
110 | |
111 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, | |
112 bool isVarArg, | |
113 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, | |
114 LLVMContext &Context) const override; | |
115 | |
116 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; | |
117 }; | |
118 | |
119 } // end namespace llvm | |
120 | |
121 #endif // LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H |