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comparison lib/Target/ARC/ARCInstrInfo.h @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
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120:1172e4bd9c6f 121:803732b1fca8
1 //===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
16
17 #include "ARCRegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h"
19
20 #define GET_INSTRINFO_HEADER
21 #include "ARCGenInstrInfo.inc"
22
23 namespace llvm {
24
25 class ARCSubtarget;
26
27 class ARCInstrInfo : public ARCGenInstrInfo {
28 const ARCRegisterInfo RI;
29 virtual void anchor();
30
31 public:
32 ARCInstrInfo();
33
34 const ARCRegisterInfo &getRegisterInfo() const { return RI; }
35
36 /// If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot. If
39 /// not, return 0. This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
41 unsigned isLoadFromStackSlot(const MachineInstr &MI,
42 int &FrameIndex) const override;
43
44 /// If the specified machine instruction is a direct
45 /// store to a stack slot, return the virtual or physical register number of
46 /// the source reg along with the FrameIndex of the loaded stack slot. If
47 /// not, return 0. This predicate must return 0 if the instruction has
48 /// any side effects other than storing to the stack slot.
49 unsigned isStoreToStackSlot(const MachineInstr &MI,
50 int &FrameIndex) const override;
51
52 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
53
54 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
55 MachineBasicBlock *&FBB,
56 SmallVectorImpl<MachineOperand> &Cond,
57 bool AllowModify) const override;
58
59 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
60 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
61 const DebugLoc &dl,
62 int *BytesAdded = nullptr) const override;
63
64 unsigned removeBranch(MachineBasicBlock &MBB,
65 int *BytesRemoved = nullptr) const override;
66
67 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
68 const DebugLoc &dl, unsigned DestReg, unsigned SrcReg,
69 bool KillSrc) const override;
70
71 void storeRegToStackSlot(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MI, unsigned SrcReg,
73 bool isKill, int FrameIndex,
74 const TargetRegisterClass *RC,
75 const TargetRegisterInfo *TRI) const override;
76
77 void loadRegFromStackSlot(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator MI, unsigned DestReg,
79 int FrameIndex, const TargetRegisterClass *RC,
80 const TargetRegisterInfo *TRI) const override;
81
82 bool
83 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
84
85 // Emit code before MBBI to load immediate value into physical register Reg.
86 // Returns an iterator to the new instruction.
87 MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MI,
89 unsigned Reg, uint64_t Value) const;
90 };
91
92 } // end namespace llvm
93
94 #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H