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comparison test/CodeGen/AArch64/fp16-v16-instructions.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents afa8332a0e37
children
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
9 ; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s 9 ; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
10 ; CHECK-DAG: fcvtn v0.4h, [[S0]] 10 ; CHECK-DAG: fcvtn v0.4h, [[S0]]
11 ; CHECK-DAG: fcvtn v1.4h, [[S2]] 11 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
12 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]] 12 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
13 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]] 13 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
14 ; CHECK-DAg: ins v0.d[1], v[[R1]].d[0] 14 ; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
15 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0] 15 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
16 16
17 %1 = sitofp <16 x i32> %a to <16 x half> 17 %1 = sitofp <16 x i32> %a to <16 x half>
18 ret <16 x half> %1 18 ret <16 x half> %1
19 } 19 }
60 ; CHECK-DAG: ucvtf [[S3:v[0-9]+\.4s]], v3.4s 60 ; CHECK-DAG: ucvtf [[S3:v[0-9]+\.4s]], v3.4s
61 ; CHECK-DAG: fcvtn v0.4h, [[S0]] 61 ; CHECK-DAG: fcvtn v0.4h, [[S0]]
62 ; CHECK-DAG: fcvtn v1.4h, [[S2]] 62 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
63 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]] 63 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
64 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]] 64 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
65 ; CHECK-DAg: ins v0.d[1], v[[R1]].d[0] 65 ; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
66 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0] 66 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
67 67
68 %1 = uitofp <16 x i32> %a to <16 x half> 68 %1 = uitofp <16 x i32> %a to <16 x half>
69 ret <16 x half> %1 69 ret <16 x half> %1
70 } 70 }