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comparison test/CodeGen/AMDGPU/mad_uint24.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children
comparison
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120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC 2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
3 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC 3 ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
4 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC 4 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC
5 ; RUN: llc < %s -march=amdgcn -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC 5 ; RUN: llc < %s -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC
6 6
7 declare i32 @llvm.r600.read.tidig.x() nounwind readnone 7 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
8 8
9 ; FUNC-LABEL: {{^}}u32_mad24: 9 ; FUNC-LABEL: {{^}}u32_mad24:
10 ; EG: MULADD_UINT24 10 ; EG: MULADD_UINT24
11 ; SI: v_mad_u32_u24 11 ; SI: v_mad_u32_u24
12 ; VI: v_mad_u32_u24 12 ; VI: v_mad_u32_u24
13 13
14 define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 14 define amdgpu_kernel void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
15 entry: 15 entry:
16 %0 = shl i32 %a, 8 16 %0 = shl i32 %a, 8
17 %a_24 = lshr i32 %0, 8 17 %a_24 = lshr i32 %0, 8
18 %1 = shl i32 %b, 8 18 %1 = shl i32 %b, 8
19 %b_24 = lshr i32 %1, 8 19 %b_24 = lshr i32 %1, 8
30 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x 30 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
31 ; EG: 16 31 ; EG: 16
32 ; FIXME: Should be using scalar instructions here. 32 ; FIXME: Should be using scalar instructions here.
33 ; GCN: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} 33 ; GCN: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
34 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MAD]], 0, 16 34 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MAD]], 0, 16
35 define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) { 35 define amdgpu_kernel void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
36 entry: 36 entry:
37 %0 = mul i16 %a, %b 37 %0 = mul i16 %a, %b
38 %1 = add i16 %0, %c 38 %1 = add i16 %0, %c
39 %2 = sext i16 %1 to i32 39 %2 = sext i16 %1 to i32
40 store i32 %2, i32 addrspace(1)* %out 40 store i32 %2, i32 addrspace(1)* %out
47 ; The result must be sign-extended 47 ; The result must be sign-extended
48 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x 48 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
49 ; EG: 8 49 ; EG: 8
50 ; GCN: v_mad_u32_u24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} 50 ; GCN: v_mad_u32_u24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
51 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8 51 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
52 define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) { 52 define amdgpu_kernel void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
53 entry: 53 entry:
54 %0 = mul i8 %a, %b 54 %0 = mul i8 %a, %b
55 %1 = add i8 %0, %c 55 %1 = add i8 %0, %c
56 %2 = sext i8 %1 to i32 56 %2 = sext i8 %1 to i32
57 store i32 %2, i32 addrspace(1)* %out 57 store i32 %2, i32 addrspace(1)* %out
66 66
67 ; Check that the select instruction is not deleted. 67 ; Check that the select instruction is not deleted.
68 ; FUNC-LABEL: {{^}}i24_i32_i32_mad: 68 ; FUNC-LABEL: {{^}}i24_i32_i32_mad:
69 ; EG: CNDE_INT 69 ; EG: CNDE_INT
70 ; SI: v_cndmask 70 ; SI: v_cndmask
71 define void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { 71 define amdgpu_kernel void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
72 entry: 72 entry:
73 %0 = ashr i32 %a, 8 73 %0 = ashr i32 %a, 8
74 %1 = icmp ne i32 %c, 0 74 %1 = icmp ne i32 %c, 0
75 %2 = select i1 %1, i32 %0, i32 34 75 %2 = select i1 %1, i32 %0, i32 34
76 %3 = mul i32 %2, %c 76 %3 = mul i32 %2, %c