Members/tobaru/cbc/CbC_llvm: lib/Target/PowerPC/PPCFastISel.cpp comparison

comparison lib/Target/PowerPC/PPCFastISel.cpp @ 95:afa8332a0e37

LLVM 3.8

author	Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date	Tue, 13 Oct 2015 17:48:58 +0900
parents	60c9769439b8
children	7d135dc70f03

comparison

equal deleted inserted replaced

-:f3e34b893a5f
+:afa8332a0e37
 // Utility routines.
 private:
 bool isTypeLegal(Type *Ty, MVT &VT);
 bool isLoadTypeLegal(Type *Ty, MVT &VT);
+bool isValueAvailable(const Value *V) const;
 bool isVSFRCRegister(unsigned Register) const {
 return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID;
+}
+bool isVSSRCRegister(unsigned Register) const {
+return MRI.getRegClass(Register)->getID() == PPC::VSSRCRegClassID;
 }
 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
 bool isZExt, unsigned DestReg);
 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
 const TargetRegisterClass *RC, bool IsZExt = true,
 unsigned &IndexReg);
 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
 unsigned DestReg, bool IsZExt);
 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
-unsigned PPCMaterializeInt(const Constant *C, MVT VT, bool UseSExt = true);
+unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
+bool UseSExt = true);
 unsigned PPCMaterialize32BitInt(int64_t Imm,
 const TargetRegisterClass *RC);
 unsigned PPCMaterialize64BitInt(int64_t Imm,
 const TargetRegisterClass *RC);
 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
 // Determine whether the type Ty is simple enough to be handled by
 // fast-isel, and return its equivalent machine type in VT.
 // FIXME: Copied directly from ARM -- factor into base class?
 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
-EVT Evt = TLI.getValueType(Ty, true);
+EVT Evt = TLI.getValueType(DL, Ty, true);
 // Only handle simple types.
 if (Evt == MVT::Other || !Evt.isSimple()) return false;
 VT = Evt.getSimpleVT();
 // If this is a type than can be sign or zero-extended to a basic operation
 // go ahead and accept it now.
 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
 return true;
 }
+return false;
+}
+bool PPCFastISel::isValueAvailable(const Value *V) const {
+if (!isa<Instruction>(V))
+return true;
+const auto *I = cast<Instruction>(V);
+if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
+return true;
 return false;
 }
 // Given a value Obj, create an Address object Addr that represents its
 case Instruction::BitCast:
 // Look through bitcasts.
 return PPCComputeAddress(U->getOperand(0), Addr);
 case Instruction::IntToPtr:
 // Look past no-op inttoptrs.
-if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
+if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
+TLI.getPointerTy(DL))
 return PPCComputeAddress(U->getOperand(0), Addr);
 break;
 case Instruction::PtrToInt:
 // Look past no-op ptrtoints.
-if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
+if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
 return PPCComputeAddress(U->getOperand(0), Addr);
 break;
 case Instruction::GetElementPtr: {
 Address SavedAddr = Addr;
 long TmpOffset = Addr.Offset;
 unsigned IndexReg = 0;
 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
 // If this is a potential VSX load with an offset of 0, a VSX indexed load can
 // be used.
+bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
-if (IsVSFRC && (Opc == PPC::LFD) &&
+bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
+bool Is64VSXLoad = IsVSSRC && Opc == PPC::LFD;
+if ((Is32VSXLoad || Is64VSXLoad) &&
 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
 (Addr.Offset == 0)) {
 UseOffset = false;
 }
 // Note: If we still have a frame index here, we know the offset is
 // in range, as otherwise PPCSimplifyAddress would have converted it
 // into a RegBase.
 if (Addr.BaseType == Address::FrameIndexBase) {
 // VSX only provides an indexed load.
-if (IsVSFRC && Opc == PPC::LFD) return false;
+if (Is32VSXLoad || Is64VSXLoad) return false;
-MachineMemOperand *MMO =
+MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
-FuncInfo.MF->getMachineMemOperand(
+MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
-MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
+Addr.Offset),
 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
 MFI.getObjectAlignment(Addr.Base.FI));
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
 // Base reg with offset in range.
 } else if (UseOffset) {
 // VSX only provides an indexed load.
-if (IsVSFRC && Opc == PPC::LFD) return false;
+if (Is32VSXLoad || Is64VSXLoad) return false;
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
 // Indexed form.
 case PPC::LWZ:    Opc = PPC::LWZX;    break;
 case PPC::LWZ8:   Opc = PPC::LWZX8;   break;
 case PPC::LWA:    Opc = PPC::LWAX;    break;
 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
 case PPC::LD:     Opc = PPC::LDX;     break;
-case PPC::LFS:    Opc = PPC::LFSX;    break;
+case PPC::LFS:    Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
 case PPC::LFD:    Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
 }
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
 .addReg(Addr.Base.Reg).addReg(IndexReg);
 }
 unsigned IndexReg = 0;
 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
 // If this is a potential VSX store with an offset of 0, a VSX indexed store
 // can be used.
+bool IsVSSRC = isVSSRCRegister(SrcReg);
 bool IsVSFRC = isVSFRCRegister(SrcReg);
-if (IsVSFRC && (Opc == PPC::STFD) &&
+bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
-(Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
+bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
+if ((Is32VSXStore || Is64VSXStore) &&
+(Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
 (Addr.Offset == 0)) {
 UseOffset = false;
 }
 // Note: If we still have a frame index here, we know the offset is
 // in range, as otherwise PPCSimplifyAddress would have converted it
 // into a RegBase.
 if (Addr.BaseType == Address::FrameIndexBase) {
 // VSX only provides an indexed store.
-if (IsVSFRC && Opc == PPC::STFD) return false;
+if (Is32VSXStore || Is64VSXStore) return false;
-MachineMemOperand *MMO =
+MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
-FuncInfo.MF->getMachineMemOperand(
+MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
-MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
+Addr.Offset),
 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
 MFI.getObjectAlignment(Addr.Base.FI));
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
 .addReg(SrcReg)
 .addMemOperand(MMO);
 // Base reg with offset in range.
 } else if (UseOffset) {
 // VSX only provides an indexed store.
-if (IsVSFRC && Opc == PPC::STFD) return false;
+if (Is32VSXStore || Is64VSXStore) return false;
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
 // Indexed form.
 case PPC::STW : Opc = PPC::STWX;  break;
 case PPC::STB8: Opc = PPC::STBX8; break;
 case PPC::STH8: Opc = PPC::STHX8; break;
 case PPC::STW8: Opc = PPC::STWX8; break;
 case PPC::STD:  Opc = PPC::STDX;  break;
-case PPC::STFS: Opc = PPC::STFSX; break;
+case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
 }
-BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
-.addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
+auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
+.addReg(SrcReg);
+// If we have an index register defined we use it in the store inst,
+// otherwise we use X0 as base as it makes the vector instructions to
+// use zero in the computation of the effective address regardless the
+// content of the register.
+if (IndexReg)
+MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
+else
+MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
 }
 return true;
 }
 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
 // For now, just try the simplest case where it's fed by a compare.
 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
-Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
+if (isValueAvailable(CI)) {
-if (!OptPPCPred)
+Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
-return false;
+if (!OptPPCPred)
+return false;
-PPC::Predicate PPCPred = OptPPCPred.getValue();
+PPC::Predicate PPCPred = OptPPCPred.getValue();
-// Take advantage of fall-through opportunities.
-if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
+// Take advantage of fall-through opportunities.
-std::swap(TBB, FBB);
+if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
-PPCPred = PPC::InvertPredicate(PPCPred);
+std::swap(TBB, FBB);
+PPCPred = PPC::InvertPredicate(PPCPred);
+}
+unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
+if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
+CondReg))
+return false;
+BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
+.addImm(PPCPred).addReg(CondReg).addMBB(TBB);
+finishCondBranch(BI->getParent(), TBB, FBB);
+return true;
 }
-unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
-if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
-CondReg))
-return false;
-BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
-.addImm(PPCPred).addReg(CondReg).addMBB(TBB);
-fastEmitBranch(FBB, DbgLoc);
-FuncInfo.MBB->addSuccessor(TBB);
-return true;
 } else if (const ConstantInt *CI =
 dyn_cast<ConstantInt>(BI->getCondition())) {
 uint64_t Imm = CI->getZExtValue();
 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
 fastEmitBranch(Target, DbgLoc);
 // Attempt to emit a compare of the two source values.  Signed and unsigned
 // comparisons are supported.  Return false if we can't handle it.
 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
 bool IsZExt, unsigned DestReg) {
 Type *Ty = SrcValue1->getType();
-EVT SrcEVT = TLI.getValueType(Ty, true);
+EVT SrcEVT = TLI.getValueType(DL, Ty, true);
 if (!SrcEVT.isSimple())
 return false;
 MVT SrcVT = SrcEVT.getSimpleVT();
 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
 }
 // Attempt to fast-select a floating-point extend instruction.
 bool PPCFastISel::SelectFPExt(const Instruction *I) {
 Value *Src  = I->getOperand(0);
-EVT SrcVT  = TLI.getValueType(Src->getType(), true);
+EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
-EVT DestVT = TLI.getValueType(I->getType(), true);
+EVT DestVT = TLI.getValueType(DL, I->getType(), true);
 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
 return false;
 unsigned SrcReg = getRegForValue(Src);
 }
 // Attempt to fast-select a floating-point truncate instruction.
 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
 Value *Src  = I->getOperand(0);
-EVT SrcVT  = TLI.getValueType(Src->getType(), true);
+EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
-EVT DestVT = TLI.getValueType(I->getType(), true);
+EVT DestVT = TLI.getValueType(DL, I->getType(), true);
 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
 return false;
 unsigned SrcReg = getRegForValue(Src);
 return ResultReg;
 }
 // Attempt to fast-select an integer-to-floating-point conversion.
+// FIXME: Once fast-isel has better support for VSX, conversions using
+//        direct moves should be implemented.
 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
 MVT DstVT;
 Type *DstTy = I->getType();
 if (!isTypeLegal(DstTy, DstVT))
 return false;
 if (DstVT != MVT::f32 && DstVT != MVT::f64)
 return false;
 Value *Src = I->getOperand(0);
-EVT SrcEVT = TLI.getValueType(Src->getType(), true);
+EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
 if (!SrcEVT.isSimple())
 return false;
 MVT SrcVT = SrcEVT.getSimpleVT();
 return ResultReg;
 }
 // Attempt to fast-select a floating-point-to-integer conversion.
+// FIXME: Once fast-isel has better support for VSX, conversions using
+//        direct moves should be implemented.
 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
 MVT DstVT, SrcVT;
 Type *DstTy = I->getType();
 if (!isTypeLegal(DstTy, DstVT))
 return false;
 }
 // Attempt to fast-select a binary integer operation that isn't already
 // handled automatically.
 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
-EVT DestVT  = TLI.getValueType(I->getType(), true);
+EVT DestVT = TLI.getValueType(DL, I->getType(), true);
 // We can get here in the case when we have a binary operation on a non-legal
 // type and the target independent selector doesn't know how to handle it.
 if (DestVT != MVT::i16 && DestVT != MVT::i8)
 return false;
 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
 CallingConv::ID CC  = CLI.CallConv;
 bool IsTailCall     = CLI.IsTailCall;
 bool IsVarArg       = CLI.IsVarArg;
 const Value *Callee = CLI.Callee;
-const char *SymName = CLI.SymName;
+const MCSymbol *Symbol = CLI.Symbol;
-if (!Callee && !SymName)
+if (!Callee && !Symbol)
 return false;
 // Allow SelectionDAG isel to handle tail calls.
 if (IsTailCall)
 return false;
 MVT RetVT;
 if (RetTy->isVoidTy())
 RetVT = MVT::isVoid;
 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
 RetVT != MVT::i8)
+return false;
+else if (RetVT == MVT::i1 && PPCSubTarget->useCRBits())
+// We can't handle boolean returns when CR bits are in use.
 return false;
 // FIXME: No multi-register return values yet.
 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
 PPCFuncInfo->setUsesTOCBasePtr();
 MIB.addReg(PPC::X2, RegState::Implicit);
 // Add a register mask with the call-preserved registers.  Proper
 // defs for return values will be added by setPhysRegsDeadExcept().
-MIB.addRegMask(TRI.getCallPreservedMask(CC));
+MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
 CLI.Call = MIB;
 // Finish off the call including any return values.
 return finishCall(RetVT, CLI, NumBytes);
 SmallVector<unsigned, 4> RetRegs;
 CallingConv::ID CC = F.getCallingConv();
 if (Ret->getNumOperands() > 0) {
 SmallVector<ISD::OutputArg, 4> Outs;
-GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
+GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
 // Analyze operands of the call, assigning locations to each operand.
 SmallVector<CCValAssign, 16> ValLocs;
 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
 // FIXME: Only one output register for now.
 if (ValLocs.size() > 1)
 return false;
-// Special case for returning a constant integer of any size.
+// Special case for returning a constant integer of any size - materialize
-// Materialize the constant as an i64 and copy it to the return
+// the constant as an i64 and copy it to the return register.
-// register. We still need to worry about properly extending the sign. E.g:
+if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
-// If the constant has only one bit, it means it is a boolean. Therefore
-// we can't use PPCMaterializeInt because it extends the sign which will
-// cause negations of the returned value to be incorrect as they are
-// implemented as the flip of the least significant bit.
-if (isa<ConstantInt>(*RV)) {
-const Constant *C = cast<Constant>(RV);
 CCValAssign &VA = ValLocs[0];
 unsigned RetReg = VA.getLocReg();
-unsigned SrcReg = PPCMaterializeInt(C, MVT::i64,
+// We still need to worry about properly extending the sign. For example,
-VA.getLocInfo() == CCValAssign::SExt);
+// we could have only a single bit or a constant that needs zero
+// extension rather than sign extension. Make sure we pass the return
+// value extension property to integer materialization.
+unsigned SrcReg =
+PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() == CCValAssign::SExt);
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
 RetRegs.push_back(RetReg);
 CCValAssign &VA = ValLocs[i];
 assert(VA.isRegLoc() && "Can only return in registers!");
 RetRegs.push_back(VA.getLocReg());
 unsigned SrcReg = Reg + VA.getValNo();
-EVT RVEVT = TLI.getValueType(RV->getType());
+EVT RVEVT = TLI.getValueType(DL, RV->getType());
 if (!RVEVT.isSimple())
 return false;
 MVT RVVT = RVEVT.getSimpleVT();
 MVT DestVT = VA.getLocVT();
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
 .addReg(AddrReg);
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
-for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
+for (const BasicBlock *SuccBB : IB->successors())
-FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
+FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
 return true;
 }
 // Attempt to fast-select an integer truncate instruction.
 bool PPCFastISel::SelectTrunc(const Instruction *I) {
 Value *Src  = I->getOperand(0);
-EVT SrcVT  = TLI.getValueType(Src->getType(), true);
+EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
-EVT DestVT = TLI.getValueType(I->getType(), true);
+EVT DestVT = TLI.getValueType(DL, I->getType(), true);
 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
 return false;
 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
 bool IsZExt = isa<ZExtInst>(I);
 unsigned SrcReg = getRegForValue(Src);
 if (!SrcReg) return false;
 EVT SrcEVT, DestEVT;
-SrcEVT = TLI.getValueType(SrcTy, true);
+SrcEVT = TLI.getValueType(DL, SrcTy, true);
-DestEVT = TLI.getValueType(DestTy, true);
+DestEVT = TLI.getValueType(DL, DestTy, true);
 if (!SrcEVT.isSimple())
 return false;
 if (!DestEVT.isSimple())
 return false;
 assert(Align > 0 && "Unexpectedly missing alignment information!");
 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
 CodeModel::Model CModel = TM.getCodeModel();
-MachineMemOperand *MMO =
+MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
-FuncInfo.MF->getMachineMemOperand(
+MachinePointerInfo::getConstantPool(*FuncInfo.MF),
-MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
+MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align);
-(VT == MVT::f32) ? 4 : 8, Align);
 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
 PPCFuncInfo->setUsesTOCBasePtr();
 // If/when switches are implemented, jump tables should be handled
 // on the "if" path here.
 if (CModel == CodeModel::Large ||
 (GV->getType()->getElementType()->isFunctionTy() &&
-(GV->isDeclaration() || GV->isWeakForLinker())) ||
+!GV->isStrongDefinitionForLinker()) ||
 GV->isDeclaration() || GV->hasCommonLinkage() ||
 GV->hasAvailableExternallyLinkage())
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
 else
 }
 // Materialize an integer constant into a register, and return
 // the register number (or zero if we failed to handle it).
-unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT,
+unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
 bool UseSExt) {
 // If we're using CR bit registers for i1 values, handle that as a special
 // case first.
 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
-const ConstantInt *CI = cast<ConstantInt>(C);
 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
 return ImmReg;
 }
 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
 &PPC::GPRCRegClass);
 // If the constant is in range, use a load-immediate.
-const ConstantInt *CI = cast<ConstantInt>(C);
+if (UseSExt && isInt<16>(CI->getSExtValue())) {
-if (isInt<16>(CI->getSExtValue())) {
 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
 unsigned ImmReg = createResultReg(RC);
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
-.addImm( (UseSExt) ? CI->getSExtValue() : CI->getZExtValue() );
+.addImm(CI->getSExtValue());
+return ImmReg;
+} else if (!UseSExt && isUInt<16>(CI->getZExtValue())) {
+unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
+unsigned ImmReg = createResultReg(RC);
+BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
+.addImm(CI->getZExtValue());
 return ImmReg;
 }
 // Construct the constant piecewise.
 int64_t Imm = CI->getZExtValue();
 }
 // Materialize a constant into a register, and return the register
 // number (or zero if we failed to handle it).
 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
-EVT CEVT = TLI.getValueType(C->getType(), true);
+EVT CEVT = TLI.getValueType(DL, C->getType(), true);
 // Only handle simple types.
 if (!CEVT.isSimple()) return 0;
 MVT VT = CEVT.getSimpleVT();
 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
 return PPCMaterializeFP(CFP, VT);
 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
 return PPCMaterializeGV(GV, VT);
-else if (isa<ConstantInt>(C))
+else if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
-return PPCMaterializeInt(C, VT, VT != MVT::i1);
+return PPCMaterializeInt(CI, VT, VT != MVT::i1);
 return 0;
 }
 // Materialize the address created by an alloca into a register, and

Mercurial > hg > Members > tobaru > cbc > CbC_llvm

comparison lib/Target/PowerPC/PPCFastISel.cpp @ 95:afa8332a0e37