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comparison lib/Target/X86/X86FloatingPoint.cpp @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children 7d135dc70f03
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
30 #include "llvm/ADT/SmallPtrSet.h" 30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallSet.h" 31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h" 32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h" 33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/EdgeBundles.h" 34 #include "llvm/CodeGen/EdgeBundles.h"
35 #include "llvm/CodeGen/LivePhysRegs.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h" 36 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h" 37 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h" 38 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/LivePhysRegs.h"
39 #include "llvm/CodeGen/Passes.h" 39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/IR/InlineAsm.h" 40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/Support/Debug.h" 41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h" 42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/Support/raw_ostream.h"
118 EdgeBundles *Bundles; 118 EdgeBundles *Bundles;
119 119
120 // Return a bitmask of FP registers in block's live-in list. 120 // Return a bitmask of FP registers in block's live-in list.
121 static unsigned calcLiveInMask(MachineBasicBlock *MBB) { 121 static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
122 unsigned Mask = 0; 122 unsigned Mask = 0;
123 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 123 for (const auto &LI : MBB->liveins()) {
124 E = MBB->livein_end(); I != E; ++I) { 124 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6)
125 unsigned Reg = *I;
126 if (Reg < X86::FP0 || Reg > X86::FP6)
127 continue; 125 continue;
128 Mask |= 1 << (Reg - X86::FP0); 126 Mask |= 1 << (LI.PhysReg - X86::FP0);
129 } 127 }
130 return Mask; 128 return Mask;
131 } 129 }
132 130
133 // Partition all the CFG edges into LiveBundles. 131 // Partition all the CFG edges into LiveBundles.
298 bool FPS::runOnMachineFunction(MachineFunction &MF) { 296 bool FPS::runOnMachineFunction(MachineFunction &MF) {
299 // We only need to run this pass if there are any FP registers used in this 297 // We only need to run this pass if there are any FP registers used in this
300 // function. If it is all integer, there is nothing for us to do! 298 // function. If it is all integer, there is nothing for us to do!
301 bool FPIsUsed = false; 299 bool FPIsUsed = false;
302 300
303 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); 301 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
302 const MachineRegisterInfo &MRI = MF.getRegInfo();
304 for (unsigned i = 0; i <= 6; ++i) 303 for (unsigned i = 0; i <= 6; ++i)
305 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { 304 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
306 FPIsUsed = true; 305 FPIsUsed = true;
307 break; 306 break;
308 } 307 }
309 308
310 // Early exit. 309 // Early exit.
436 } else { 435 } else {
437 MachineBasicBlock::iterator Start = I; 436 MachineBasicBlock::iterator Start = I;
438 // Rewind to first instruction newly inserted. 437 // Rewind to first instruction newly inserted.
439 while (Start != BB.begin() && std::prev(Start) != PrevI) --Start; 438 while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
440 dbgs() << "Inserted instructions:\n\t"; 439 dbgs() << "Inserted instructions:\n\t";
441 Start->print(dbgs(), &MF.getTarget()); 440 Start->print(dbgs());
442 while (++Start != std::next(I)) {} 441 while (++Start != std::next(I)) {}
443 } 442 }
444 dumpStack(); 443 dumpStack();
445 ); 444 );
446 (void)PrevMI; 445 (void)PrevMI;
1518 1517
1519 // Don't delete the inline asm! 1518 // Don't delete the inline asm!
1520 return; 1519 return;
1521 } 1520 }
1522 1521
1523 case X86::WIN_FTOL_32:
1524 case X86::WIN_FTOL_64: {
1525 // Push the operand into ST0.
1526 MachineOperand &Op = MI->getOperand(0);
1527 assert(Op.isUse() && Op.isReg() &&
1528 Op.getReg() >= X86::FP0 && Op.getReg() <= X86::FP6);
1529 unsigned FPReg = getFPReg(Op);
1530 if (Op.isKill())
1531 moveToTop(FPReg, Inst);
1532 else
1533 duplicateToTop(FPReg, FPReg, Inst);
1534
1535 // Emit the call. This will pop the operand.
1536 BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::CALLpcrel32))
1537 .addExternalSymbol("_ftol2")
1538 .addReg(X86::ST0, RegState::ImplicitKill)
1539 .addReg(X86::ECX, RegState::ImplicitDefine)
1540 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
1541 .addReg(X86::EDX, RegState::Define | RegState::Implicit)
1542 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1543 --StackTop;
1544
1545 break;
1546 }
1547
1548 case X86::RETQ: 1522 case X86::RETQ:
1549 case X86::RETL: 1523 case X86::RETL:
1550 case X86::RETIL: 1524 case X86::RETIL:
1551 case X86::RETIQ: 1525 case X86::RETIQ:
1552 // If RET has an FP register use operand, pass the first one in ST(0) and 1526 // If RET has an FP register use operand, pass the first one in ST(0) and