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comparison test/CodeGen/AArch64/arm64-anyregcc.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
53 ; CHECK-NEXT: .byte 8 53 ; CHECK-NEXT: .byte 8
54 ; CHECK-NEXT: .short 0 54 ; CHECK-NEXT: .short 0
55 ; CHECK-NEXT: .long 3 55 ; CHECK-NEXT: .long 3
56 define i64 @test() nounwind ssp uwtable { 56 define i64 @test() nounwind ssp uwtable {
57 entry: 57 entry:
58 call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3) 58 call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
59 ret i64 0 59 ret i64 0
60 } 60 }
61 61
62 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register 62 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
63 ; CHECK-LABEL: .long L{{.*}}-_property_access1 63 ; CHECK-LABEL: .long L{{.*}}-_property_access1
75 ; CHECK-NEXT: .short {{[0-9]+}} 75 ; CHECK-NEXT: .short {{[0-9]+}}
76 ; CHECK-NEXT: .long 0 76 ; CHECK-NEXT: .long 0
77 define i64 @property_access1(i8* %obj) nounwind ssp uwtable { 77 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
78 entry: 78 entry:
79 %f = inttoptr i64 281474417671919 to i8* 79 %f = inttoptr i64 281474417671919 to i8*
80 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj) 80 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
81 ret i64 %ret 81 ret i64 %ret
82 } 82 }
83 83
84 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register 84 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
85 ; CHECK-LABEL: .long L{{.*}}-_property_access2 85 ; CHECK-LABEL: .long L{{.*}}-_property_access2
98 ; CHECK-NEXT: .long 0 98 ; CHECK-NEXT: .long 0
99 define i64 @property_access2() nounwind ssp uwtable { 99 define i64 @property_access2() nounwind ssp uwtable {
100 entry: 100 entry:
101 %obj = alloca i64, align 8 101 %obj = alloca i64, align 8
102 %f = inttoptr i64 281474417671919 to i8* 102 %f = inttoptr i64 281474417671919 to i8*
103 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj) 103 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
104 ret i64 %ret 104 ret i64 %ret
105 } 105 }
106 106
107 ; property access 3 - %obj is a frame index 107 ; property access 3 - %obj is a frame index
108 ; CHECK-LABEL: .long L{{.*}}-_property_access3 108 ; CHECK-LABEL: .long L{{.*}}-_property_access3
121 ; CHECK-NEXT: .long -8 121 ; CHECK-NEXT: .long -8
122 define i64 @property_access3() nounwind ssp uwtable { 122 define i64 @property_access3() nounwind ssp uwtable {
123 entry: 123 entry:
124 %obj = alloca i64, align 8 124 %obj = alloca i64, align 8
125 %f = inttoptr i64 281474417671919 to i8* 125 %f = inttoptr i64 281474417671919 to i8*
126 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj) 126 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
127 ret i64 %ret 127 ret i64 %ret
128 } 128 }
129 129
130 ; anyreg_test1 130 ; anyreg_test1
131 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test1 131 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
203 ; CHECK-NEXT: .short {{[0-9]+}} 203 ; CHECK-NEXT: .short {{[0-9]+}}
204 ; CHECK-NEXT: .long 0 204 ; CHECK-NEXT: .long 0
205 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { 205 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
206 entry: 206 entry:
207 %f = inttoptr i64 281474417671919 to i8* 207 %f = inttoptr i64 281474417671919 to i8*
208 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) 208 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
209 ret i64 %ret 209 ret i64 %ret
210 } 210 }
211 211
212 ; anyreg_test2 212 ; anyreg_test2
213 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test2 213 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
285 ; CHECK-NEXT: .short {{[0-9]+}} 285 ; CHECK-NEXT: .short {{[0-9]+}}
286 ; CHECK-NEXT: .long 0 286 ; CHECK-NEXT: .long 0
287 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { 287 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
288 entry: 288 entry:
289 %f = inttoptr i64 281474417671919 to i8* 289 %f = inttoptr i64 281474417671919 to i8*
290 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) 290 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
291 ret i64 %ret 291 ret i64 %ret
292 } 292 }
293 293
294 ; Test spilling the return value of an anyregcc call. 294 ; Test spilling the return value of an anyregcc call.
295 ; 295 ;
313 ; CHECK-NEXT: .byte 8 313 ; CHECK-NEXT: .byte 8
314 ; CHECK-NEXT: .short {{[0-9]+}} 314 ; CHECK-NEXT: .short {{[0-9]+}}
315 ; CHECK-NEXT: .long 0 315 ; CHECK-NEXT: .long 0
316 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { 316 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
317 entry: 317 entry:
318 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2) 318 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
319 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind 319 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
320 ret i64 %result 320 ret i64 %result
321 } 321 }
322 322
323 ; Test spilling the arguments of an anyregcc call. 323 ; Test spilling the arguments of an anyregcc call.
353 ; CHECK-NEXT: .short 29 353 ; CHECK-NEXT: .short 29
354 ; CHECK-NEXT: .long -88 354 ; CHECK-NEXT: .long -88
355 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { 355 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
356 entry: 356 entry:
357 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind 357 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
358 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4) 358 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
359 ret i64 %result 359 ret i64 %result
360 } 360 }
361 361
362 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) 362 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
363 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) 363 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)