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comparison test/CodeGen/AArch64/arm64-umaxv.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
2 2
3 define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp { 3 define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
4 ; CHECK-LABEL: vmax_u8x8: 4 ; CHECK-LABEL: vmax_u8x8:
5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0 5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
6 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]] 6 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
84 return: 84 return:
85 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 85 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
86 ret i32 %retval.0 86 ret i32 %retval.0
87 } 87 }
88 88
89 define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
90 ; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:
91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
92 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
93 ; CHECK-NEXT: ret
94 entry:
95 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
96 %1 = trunc i32 %0 to i8
97 %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
98 ret <8 x i8> %2
99 }
100
101 define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
102 ; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:
103 ; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
104 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
105 ; CHECK-NEXT: ret
106 entry:
107 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)
108 %1 = trunc i32 %0 to i16
109 %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
110 ret <4 x i16> %2
111 }
112
113 define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
114 ; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:
115 ; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
116 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
117 ; CHECK-NEXT: ret
118 entry:
119 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)
120 %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
121 ret <2 x i32> %1
122 }
123
124 define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
125 ; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:
126 ; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
127 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
128 ; CHECK-NEXT: ret
129 entry:
130 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)
131 %1 = trunc i32 %0 to i8
132 %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
133 ret <16 x i8> %2
134 }
135
136 define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
137 ; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop:
138 ; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
139 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
140 ; CHECK-NEXT: ret
141 entry:
142 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)
143 %1 = trunc i32 %0 to i16
144 %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
145 ret <8 x i16> %2
146 }
147
148 define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
149 ; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop:
150 ; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1
151 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
152 ; CHECK-NEXT: ret
153 entry:
154 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)
155 %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
156 ret <4 x i32> %1
157 }
158
89 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone 159 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone
90 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone 160 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone
91 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone 161 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone
92 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone 162 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone
163 declare i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32>) nounwind readnone
164 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>) nounwind readnone