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comparison test/CodeGen/AMDGPU/llvm.pow.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents test/CodeGen/R600/llvm.pow.ll@54457678186b
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
2
3 ;CHECK-LABEL: test1:
4 ;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
5 ;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
6 ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
7
8 define void @test1(<4 x float> inreg %reg0) #0 {
9 %r0 = extractelement <4 x float> %reg0, i32 0
10 %r1 = extractelement <4 x float> %reg0, i32 1
11 %r2 = call float @llvm.pow.f32( float %r0, float %r1)
12 %vec = insertelement <4 x float> undef, float %r2, i32 0
13 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
14 ret void
15 }
16
17 ;CHECK-LABEL: test2:
18 ;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
19 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
20 ;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
21 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
22 ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
23 ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
24 ;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
25 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
26 ;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
27 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
28 ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
29 ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
30 define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
31 %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
32 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
33 ret void
34 }
35
36 declare float @llvm.pow.f32(float ,float ) readonly
37 declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly
38 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
39
40 attributes #0 = { "ShaderType"="0" }