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comparison test/CodeGen/AMDGPU/rotr.i64.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents
children 803732b1fca8
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84:f3e34b893a5f 95:afa8332a0e37
1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s
3
4 ; BOTH-LABEL: {{^}}s_rotr_i64:
5 ; BOTH-DAG: s_sub_i32
6 ; BOTH-DAG: s_lshr_b64
7 ; BOTH-DAG: s_lshl_b64
8 ; BOTH: s_or_b64
9 define void @s_rotr_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) {
10 entry:
11 %tmp0 = sub i64 64, %y
12 %tmp1 = shl i64 %x, %tmp0
13 %tmp2 = lshr i64 %x, %y
14 %tmp3 = or i64 %tmp1, %tmp2
15 store i64 %tmp3, i64 addrspace(1)* %in
16 ret void
17 }
18
19 ; BOTH-LABEL: {{^}}v_rotr_i64:
20 ; BOTH-DAG: v_sub_i32
21 ; SI-DAG: v_lshr_b64
22 ; SI-DAG: v_lshl_b64
23 ; VI-DAG: v_lshrrev_b64
24 ; VI-DAG: v_lshlrev_b64
25 ; BOTH: v_or_b32
26 ; BOTH: v_or_b32
27 define void @v_rotr_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) {
28 entry:
29 %x = load i64, i64 addrspace(1)* %xptr, align 8
30 %y = load i64, i64 addrspace(1)* %yptr, align 8
31 %tmp0 = sub i64 64, %y
32 %tmp1 = shl i64 %x, %tmp0
33 %tmp2 = lshr i64 %x, %y
34 %tmp3 = or i64 %tmp1, %tmp2
35 store i64 %tmp3, i64 addrspace(1)* %in
36 ret void
37 }
38
39 ; BOTH-LABEL: {{^}}s_rotr_v2i64:
40 define void @s_rotr_v2i64(<2 x i64> addrspace(1)* %in, <2 x i64> %x, <2 x i64> %y) {
41 entry:
42 %tmp0 = sub <2 x i64> <i64 64, i64 64>, %y
43 %tmp1 = shl <2 x i64> %x, %tmp0
44 %tmp2 = lshr <2 x i64> %x, %y
45 %tmp3 = or <2 x i64> %tmp1, %tmp2
46 store <2 x i64> %tmp3, <2 x i64> addrspace(1)* %in
47 ret void
48 }
49
50 ; BOTH-LABEL: {{^}}v_rotr_v2i64:
51 define void @v_rotr_v2i64(<2 x i64> addrspace(1)* %in, <2 x i64> addrspace(1)* %xptr, <2 x i64> addrspace(1)* %yptr) {
52 entry:
53 %x = load <2 x i64>, <2 x i64> addrspace(1)* %xptr, align 8
54 %y = load <2 x i64>, <2 x i64> addrspace(1)* %yptr, align 8
55 %tmp0 = sub <2 x i64> <i64 64, i64 64>, %y
56 %tmp1 = shl <2 x i64> %x, %tmp0
57 %tmp2 = lshr <2 x i64> %x, %y
58 %tmp3 = or <2 x i64> %tmp1, %tmp2
59 store <2 x i64> %tmp3, <2 x i64> addrspace(1)* %in
60 ret void
61 }