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comparison test/CodeGen/AMDGPU/texture-input-merge.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents test/CodeGen/R600/texture-input-merge.ll@95c75e76d11b
children 7d135dc70f03
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
2
3 ;CHECK-NOT: MOV
4
5 define void @test(<4 x float> inreg %reg0) #0 {
6 %1 = extractelement <4 x float> %reg0, i32 0
7 %2 = extractelement <4 x float> %reg0, i32 1
8 %3 = extractelement <4 x float> %reg0, i32 2
9 %4 = extractelement <4 x float> %reg0, i32 3
10 %5 = fmul float %1, 3.0
11 %6 = fmul float %2, 3.0
12 %7 = fmul float %3, 3.0
13 %8 = fmul float %4, 3.0
14 %9 = insertelement <4 x float> undef, float %5, i32 0
15 %10 = insertelement <4 x float> %9, float %6, i32 1
16 %11 = insertelement <4 x float> undef, float %7, i32 0
17 %12 = insertelement <4 x float> %11, float %5, i32 1
18 %13 = insertelement <4 x float> undef, float %8, i32 0
19 %14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
20 %15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
21 %16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
22 %17 = fadd <4 x float> %14, %15
23 %18 = fadd <4 x float> %17, %16
24 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0)
25 ret void
26 }
27
28 declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
29 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
30
31 attributes #0 = { "ShaderType"="1" }